User manual

5.3.2.3 Changing PLL Multiplier
5.3.2.4 Changing SYSCLK Dividers
PLL2 Control www.ti.com
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization time
is previously met (step 7 in Section 5.3.2.2 ), follow this procedure to change PLL2 multiplier.
1. Before changing the PLL frequency, switch to PLL bypass mode:
a. Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
b. Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).
c. Wait for 20 MXI clock cycles to ensure PLLC switches to bypass mode properly.
2. Set the PLLRST bit in PLLCTL to 1 (reset PLL).
3. Clear the PLLDIS bit in PLLCTL to 0 (enable the PLL) to allow PLL outputs to start toggling. Note that
the PLLC is still at PLL bypass mode; therefore, the toggling PLL output does not get propagated to
the rest of the device.
4. Program the required multiplier value in the PLL multiplier control register (PLLM).
5. If necessary, program the PLL controller divider 1 register (PLLDIV1) to change the SYSCLK1 divide
value:
a. Program the RATIO field in PLLDIV1 with the desired divide factor.
b. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.
c. Wait for the GOSTAT bit in the PLL controller status register (PLLSTAT) to clear to 0 (completion of
phase alignment).
6. Wait for PLL to reset properly. The PLL reset time is a minimum of 32 MXI clock cycles.
7. Clear the PLLRST bit in PLLCTL to 0 to bring the PLL out of reset.
8. Wait for 2000 MXI clock or reference clock cycles to allow PLL to lock.
9. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.
This section discusses the software sequence to change the SYSCLK dividers. The SYSCLK divider
change sequence is also referred to as GO operation, as it involves hitting the GO bit (GOSET bit in
PLLCMD) to initiate the divider change.
1. Check for the GOSTAT bit in the PLL controller status register (PLLSTAT) to clear to 0 to indicate that
no GO operation is currently in progress.
2. Program the RATIO field in the PLL controller divider 1 register (PLLDIV1) with the desired divide
factor.
3. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.
4. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).
Note: On the DM646x DMSoC, all PLL1 SYSCLK n dividers are programmable but you should not
change the divider value to maintain the clock ratios between various modules of the device.
You should only use the power-up default divider values for all PLL1 SYSCLK n dividers for
normal device operation.
PLL2 SYSCLK1 divider value is programmable and you may change the divider value for the
desired DDR2 memory controller clock frequency.
44 PLL Controller SPRUEP9A – May 2008
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