User manual

5.1 PLL Module
PLL Module www.ti.com
The TMS320DM646x DMSoC has two PLL controllers that provide clocks to different parts of the system
(see Figure 5-1 ). PLL1 provides clocks (though various dividers) to most of the components of the
DMSoC. PLL2 is dedicated to the DDR2 memory controller. The recommended reference clock is a
27-MHZ crystal input. See the device-specific data manual for the supported input clocks.
The PLL controller provides the following:
• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power down
The various clock outputs given by the controller are:
• Domain Clocks: SYSCLK [1:n]
• Auxiliary Clock from reference clock source: AUXCLK
• Bypass Domain clock: SYSCLKBP
Various dividers that can be used are:
• SYSCLK Divider: D1, … , Dn
• SYSCLKBP Divider: BPDIV
Various other controls supported are:
• PLL Multiplier Control: PLLM
• Software programmable PLL Bypass: PLLEN
PLL Controller36 SPRUEP9A – May 2008
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