User manual

4.2.2.4 Peripheral Component Interface (PCI)
4.2.2.5 Host Port Interface (HPI)
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The PCI module allows communication with devices complaint to the PCI Local Bus Specification (revision
2.3) via a 32-bit address/data bus operating at speeds up to 33 MHZ.
The PCI module supports the following features:
• PCI Local Bus Specification (revision 2.3) compliant
• Single function PCI interface provided
• 32-bit address/data bus width
• Operation up to 33 MHZ
• Optimized burst behavior supported for system cache line sizes of 16, 32, 64 and 128 bytes
• PCI is only accessible from the ARM
The HPI provides a parallel port interface through which an external host processor can directly access
the TMS320DM646x DMSoC processor's resources (configuration and program/data memories). The
external host device is asynchronous to the CPU clock and functions as a master to the HPI interface. The
HPI enables a host device and the DM646x DMSoC processor to exchange information via internal or
external memory. Dedicated address (HPIA) and data (HPID) registers within the HPI provide the data
path between the external host interface and the processor resources. An HPI control register (HPIC) is
available to the host and the CPU for various configuration and interrupt functions.
The HPI supports the following features:
• Multiplexed address/data
• Dual 16-bit halfword cycle access (internal data word is 32-bits wide)
• 16-bit-wide host data bus interface
• Internal data bursting using 8-word read and write first-in, first-out (FIFO) buffers
• HPI control register (HPIC) accessible by both the ARM CPU and the external host
• HPI address register (HPIA) accessible by both the ARM CPU and the external host
• Separate HPI address registers for read (HPIAR) and write (HPIAW) with configurable option for
operating as a single HPI address register
• HPI data register (HPID)/FIFOs providing data-path between external host interface and CPU
resources
• Multiple strobes and control signals to allow flexible host connection
• Asynchronous HRDY output to allow the HPI to insert wait states to the host
• Software control of data prefetching to the HPID/FIFOs
• Processor-to-Host interrupt output signal controlled by HPIC accesses
• Host-to-Processor interrupt controlled by HPIC accesses
• Register controlled HPIA and HPIC ownership and FIFO timeout
• Memory-mapped peripheral identification register (PID)
• Bus holders on host data and address buses (these are actually external to HPI module)
• 32-bit word cycle access (internal data word is 32-bits wide)
• 32-bit-wide host data bus interface
SPRUEP9A – May 2008 System Memory 33
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