User manual

4.1 Memory Map
4.1.1 ARM Internal Memories
4.1.2 External Memories
4.1.3 DSP Memories
4.1.4 Peripherals
Memory Map www.ti.com
The TMS320DM646x DMSoC has multiple on-chip memories associated with its two processors and
various subsystems. To help simplify software development, a unified memory map is used where
possible to maintain a consistent view of device resources across all bus masters.
For detailed memory-map information, see the device-specific data manual.
The ARM has access to the following ARM internal memories:
• 32 KB ARM Internal RAM on TCM interface, logically separated into two 16-KB pages to allow
simultaneous access on any given cycle, if there are separate accesses for code (I-TCM bus) and data
(D-TCM) to the different memory regions.
• 8 KB ARM Internal ROM
The ARM has access to the following external memories:
• DDR2 synchronous DRAM
• Asynchronous EMIF / NOR / NAND Flash
• ATA
These memory interfaces are described in Section 1.1 .
For documentation related to these interfaces, see the Related Documentation section at the beginning of
this document.
The ARM has access to the following DSP memories:
• L2 RAM (Level 2 RAM)
• L1P RAM (Level 1 Program RAM)
• L1D RAM (Level 1 Data RAM)
The ARM has access to the following peripherals:
• Asynchronous EMIF (EMIFA)
• ATA Controller
• 2 Clock Reference Generators (CRGEN)
• DDR2 Memory Controller
• Enhanced DMA (EDMA) Controller
• Ethernet Media Access Controller (EMAC)
• General-Purpose Input/Output (GPIO)
• Host Port Interface (HPI)
• Inter-IC Communication (I2C)
• 2 Multichannel Audio Serial Ports (McASP)
• Peripheral Component Interface (PCI)
• 2 Pulse Width Modulators (PWM)
• Serial Port Interface (SPI) up to 40 MHZ with 2 chip selects
• 2 timers that are configurable as two 64-bit or four 32-bit timers and one 64-bit watchdog timer
• Transport Stream Interface (TSIF)
30 System Memory SPRUEP9A – May 2008
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