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3.7 Tightly-Coupled Memory
Tightly-Coupled Memory www.ti.com
The ARM926EJ-S has a tightly-coupled memory interface enabling separate instruction and data TCM to
be interfaced to the ARM. TCMs are meant for storing real-time and performance critical code.
The DM646x DMSoC supports both instruction TCM (I-TCM) and data TCM (D-TCM). The instruction
TCM is located at 0000:0000h to 0000:9FFFh; the data TCM is located at 0001:0000h to 0001:9FFFh, as
shown in Table 3-3 .
Table 3-3. ITCM/DTCM Memory Map
I-TCM Address D-TCM Address Size (Bytes) Description
0000:0000h - 0000:3FFFh 0001:0000h - 0001:3FFFh 16K RAM0
0000:4000h - 0000:7FFFh 0001:4000h - 0001:7FFFh 16K RAM1
0000:8000h - 0000:9FFFh 0001:8000h - 0001:9FFFh 8K ROM
0000:A000h - 0000:FFFFh 0001:A000h - 0001:FFFFh 24K Reserved
The status of the TCM memory regions can be read from the TCM status register, which is CP15 register
0. The instruction for reading the TCM status is:
MRC p15, #0, Rd, c0, c0, #2 ; read TCM status register
where Rd is any register where the status data is read into the register.
The format of the data in the TCM status register is shown in Figure 3-1 .
Figure 3-1. TCM Status Register
31 17 16
Reserved DTCM
15 1 0
Reserved ITCM
Table 3-4. TCM Status Register Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Reserved
16 DTCM Data TCM.
0 Data TCM is not present.
1 Data TCM is present.
15-1 Reserved 0 Reserved
0 ITCM Instruction TCM.
0 Instruction TCM is not present.
1 Instruction TCM is present.
26 ARM Core SPRUEP9A – May 2008
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