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3.4 Exceptions and Exception Vectors
Exceptions and Exception Vectors www.ti.com
Exceptions arise when the normal flow of the program must be temporarily halted. The exceptions that
occur in an ARM system are given below:
• Reset exception: processor reset
• FIQ interrupt: fast interrupt
• IRQ interrupt: normal interrupt
• Abort exception: abort indicates that the current memory access could not be completed. The abort
could be a pre-fetch abort or a data abort.
• SWI interrupt: use software interrupt to enter supervisor mode.
• Undefined exception: occurs when the processor executes an undefined instruction
The exceptions in the order of highest priority to lowest priority are: reset, data abort, FIQ, IRQ, pre-fetch
abort, undefined instruction, and SWI. SWI and undefined instruction have the same priority. Depending
upon the status of VINTH signal or the register setting in CP15, the vector table can be located at address
0000 0000h (VINTH = 0) or at address FFFF 0000h (VINTH = 1).
Note: This is a feature of the standard ARM9 code. However, there is no memory in the DMSoC in
this address region, so do not set this bit.
The default vector table is shown in Table 3-1
Table 3-1. Exception Vector Table for ARM
Vector Offset Address Exception Mode on entry I Bit State on Entry F Bit State on Entry
0h Reset Supervisor Set Set
4h Undefined instruction Undefined Set Unchanged
8h Software interrupt Supervisor Set Unchanged
Ch Pre-fetch abort Abort Set Unchanged
10h Data abort Abort Set Unchanged
14h Reserved - - -
18h IRQ IRQ Set Unchanged
1Ch FIQ FIQ Set Set
ARM Core22 SPRUEP9A – May 2008
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