User manual

3.2 Operating States/Modes

3.3 Processor Status Registers

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Operating States/Modes

The ARM can operate in two states: ARM (32-bit) mode and Thumb (16-bit) mode. You can switch the

ARM926EJ-S processor between ARM mode and Thumb mode using the BX instruction.

The ARM can operate in the following modes:

• User mode (USR): Non-privileged mode, usually for the execution of most application programs.

• Fast interrupt mode (FIQ): Fast interrupt processing

• Interrupt mode (IRQ): Normal interrupt processing

• Supervisor mode (SVC): Protected mode of execution for operating systems

• Abort mode (ABT): Mode of execution after a data abort or a pre-fetch abort

• System mode (SYS): Privileged mode of execution for operating systems

• Undefined mode (UND): Executing an undefined instruction causes the ARM to enter undefined mode.

You can only enter privileged modes (system or supervisor) from other privileged modes.

To enter supervisor mode from user mode, generate a software interrupt (SWI). An IRQ interrupt causes

the processor to enter the IRQ mode. An FIQ interrupt causes the processor to enter the FIQ mode.

Different stacks must be set up for different modes. The stack pointer (SP) automatically changes to the

SP of the mode that was entered.

The processor status register (PSR) controls the enabling and disabling of interrupts and setting the mode

of operation of the processor. The 8 least-significant bits, PSR[7:0], are the control bits of the processor.

PSR[27:8] are reserved bits and PSR[31:28] are status bits. The details of the control bits are:

• Bit 7 - I bit: Disable IRQ (I =1) or enable IRQ (I = 0)

• Bit 6 - F bit: Disable FIQ (F = 1) or enable FIQ (F = 0)

• Bit 5 - T bit: Controls whether the processor is in thumb mode (T = 1) or ARM mode (T = 0)

• Bits 4:0 Mode: Controls the mode of operation of the processor

– PSR [4:0] = 10000 : User mode

– PSR [4:0] = 10001 : FIQ mode

– PSR [4:0] = 10010 : IRQ mode

– PSR [4:0] = 10011 : Supervisor mode

– PSR [4:0] = 10111 : Abort mode

– PSR [4:0] = 11011 : Undefined mode

– PSR [4:0] = 11111 : System mode

Status bits show the result of the most recent ALU operation. The details of the status bits are:

• Bit 31 - N bit: Negative or less than

• Bit 30 - Z bit: Zero

• Bit 29 - C bit: Carry or borrow

• Bit 28 - V bit: Overflow or underflow

Note: See Chapter 2 of the Programmer’s Model of the ARM926EJ-S TRM, downloadable from

http://www.arm.com/arm/TRMs for more detailed information.

SPRUEP9A – May 2008 ARM Core 21

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