User manual

3.1 Introduction
Introduction www.ti.com
This chapter describes the ARM core and its associated memories. The ARM core consists of the
following components:
• ARM926EJ-S - 32-bit RISC processor
• 16-KB Instruction cache
• 8-KB Data cache
• Memory Management Unit (MMU)
• CP15 to control MMU, cache, etc.
• Java accelerator
• ARM Internal Memory
– 32 KB built-in RAM
– 8 KB built-in ROM (boot ROM)
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
• Features:
– The main write buffer has a 16-word data buffer and a 4-address buffer
– Support for 32/16-bit instruction sets
– Fixed little endian memory format
– Enhanced DSP instructions
The ARM926EJ-S processor is a member of the ARM9 family of general-purpose microprocessors. The
ARM926EJ-S processor targets multi-tasking applications where full memory management, high
performance, low die size, and low power are all important.
The ARM926EJ-S processor supports the 32-bit ARM and the 16-bit THUMB instruction sets, enabling
you to trade off between high performance and high code density. This includes features for efficient
execution of Java byte codes and providing Java performance similar to Just in Time (JIT) Java interpreter
without associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debugging. The ARM926EJ-S processor has a Harvard architecture and provides
a complete high performance subsystem, including the following:
• An ARM926EJ-S integer core
• A Memory Management Unit (MMU)
• Separate instruction and data AMBA AHB bus interfaces
• Separate instruction and data TCM interfaces
The ARM926EJ-S processor implements ARM architecture version 5TEJ.
The ARM926EJ-S core includes new signal processing extensions to enhance 16-bit fixed-point
performance using a single-cycle 32 × 16 multiply-accumulate (MAC) unit. The ARM Subsystem also has
32 KB of internal RAM and 8 KB of internal ROM, accessible via the I-TCM and D-TCM interfaces through
an arbiter. The same arbiter provides a slave DMA interface to the rest of the DM646x DMSoC.
Furthermore, the ARM has DMA and CFG bus master ports via the AHB interface.
20 ARM Core SPRUEP9A – May 2008
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