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12.5.2.2 DSP Module Clock Off
12.5.3 DSP Reset
12.5.3.1 DSP Local Reset
ARM Control of DSP Boot, Clock, and Reset www.ti.com
In the clock disable state, the DSP’s module clock is disabled while the DSP module reset remains
deasserted. This state is typically used to disable the DSP clock to save power.
• ARM: Notify the DSP to prepare for power-down.
• DSP: Prepare for power-down:
1. Set the power-down command register (PDCCMD) in the DSP power-down controller (PDC)
module to 0001 5555h
Note: PDCCMD can only be written while the DSP is in supervisor mode. See the
TMS320DM646x DMSoC DSP Subsystem Reference Guide (SPRUEP8 ) and the
TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) for more information on
the power-down controller (PDC).
2. Enable one of the interrupts: ARM2DSP0, ARM2DSP1, ARM2DSP2, ARM2DSP3, or NMI. This
interrupt wakes the DSP in the DSP clock-on sequence.
3. Execute the IDLE instruction. IDLE is a program instruction in the C64x+ CPU instruction set. When
the CPU executes IDLE, the PDC is notified and initiates DSP power-down according to the bits set
in PDCCMD. See the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) for more
information on the PDC and the IDLE instruction.
• ARM: Disable the DSP clock:
1. Wait for the GOSTAT[0] bit in the power domain transition status register (PTSTAT) in the PSC to
clear to 0. You must wait for the power domain to finish any previously initiated transitions before
initiating a new transition.
2. Set the NEXT bit in the module control 1 register (MDCTL1) in the PSC to 2h to prepare the DSP
module for a disable transition.
3. Set the GO[0] bit in the power domain transition command register (PTCMD) in the PSC to 1 to
initiate the state transition.
4. Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. The domain is only safely in the new state
after the GOSTAT[0] bit is cleared to 0.
5. Wait for the STATE bit in the module status 1 register (MDSTAT1) in the PSC to change to 2h. The
module is only safely in the new state after the STATE bit in MDSTAT1 changes to reflect the new
state.
6. Clocks to the DSP are disabled.
With access to the PSC registers, the ARM can assert and deassert DSP local reset and DSP module
reset. When DSP local reset is asserted, the DSP’s internal memories (L1P, L1D, and L2) are still
accessible. Local reset only resets the DSP CPU. Local reset is useful when the DSP module is in the
enable or disable states, since module reset is asserted in the SyncReset and SwRstDisable states and
module reset supersedes local reset. The intent of local reset is for the ARM to use local reset to reset the
DSP during the DSP boot process. The intent of module reset is for it to completely reset the DSP (like
hard reset). For more information on the PSC, see Chapter 6 . For more information on local reset and on
module reset, see Chapter 10 . This section describes how to initiate DSP local reset and module reset.
To assert/deassert local reset:
1. Clear the LRST bit in the module control 1 register (MDCTL1) in the PSC to 0 to assert DSP reset.
2. Set the LRST bit in MDCTL1 to 1 to deassert DSP reset.
ARM-DSP Integration130 SPRUEP9A – May 2008
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