User manual

12.3 Shared Memory
12.3.1 ARM Internal Memories
12.3.2 DSP Memories
12.3.3 External Memories
Shared Memory www.ti.com
The DM646x DMSoC memory-map is described in detail in Chapter 4 . As noted in Chapter 4 , ARM, DSP,
and EDMA all have access to ARM internal memory, DSP internal memory, and external memory of the
DDR2 memory controller and EMIFA. The EDMA can transfer data among shared memory without ARM
or DSP intervention. See the TMS320DM646x DMSoC Enhanced Direct Memory Access (EDMA)
Controller User's Guide (SPRUEQ5 ) for more information on the EDMA.
The ARM, DSP, and EDMA can access the ARM’s internal memories:
• 32 KB ARM internal RAM
• 8 KB ARM internal ROM
The ARM, DSP, and EDMA can access the DSP’s internal memories:
• L1P RAM (32 KB)
• L1D RAM (32 KB)
• L2 RAM (128 KB)
This feature allows the ARM and EDMA to load DSP memories with program instructions and data.
Note: Portions of the above DSP memories are configurable as DSP cache memory. When
configured as cache, neither the ARM nor the EDMA can access the cache portions. For
more information on the DSP internal memories and cache configuration, see the
TMS320DM646x DMSoC DSP Subsystem Reference Guide (SPRUEP8 ).
Both the ARM and the DSP have access to devices connected to the DDR2 memory controller and the
EMIFA. This allows the ARM and DSP to access program and data from DDR on the DDR2 memory
controller and from devices attached to the EMIFA, such as NOR flash or SRAM.
Note: The DSP can access the data space of the DDR2 memory controller and of the EMIFA.
However, the DSP cannot access the control register space of these EMIFs. Therefore, it is
the ARM's responsibility to configure the control registers of the DDR2 memory controller
and the EMIFA.
126 ARM-DSP Integration SPRUEP9A – May 2008
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