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10.4.6 DSP Boot Mode (DSP_BT) Configuration
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The DSP_BT input determines the DSP operation at reset. For most applications, the ARM is the master
device and controls the reset and boot of the DSP. Under this scenario (DSP_BT = 0), the C64x+ DSP
remains disabled (held in reset) after reset. The ARM is responsible for releasing the DSP from reset.
Before releasing the DSP from reset, the ARM must transfer a valid DSP boot image to program memory
accessible by the DSP (DSP memory, EMIFA or DDR2), and configure the DSP boot address in the DSP
boot address register (DSPBOOTADDR) in the System Module from which the C64x+ DSP begins
execution.
When DSP_BT = 1, the C64x+ DSP boots itself. Under this scenario, the C64x+ DSP is released from
reset without ARM intervention. The DSP boot address is set to an EMIFA address (4220 0000h). The
C64x+ DSP begins execution with instruction (L1P) cache enabled.
Note: The DSP_BT operation is overridden when ARM HPI or PCI boot is selected
(BOOTMODE[3:0] = 001x). This is because the ARM HPI/PCI boot selection forces the
HPIEN or PCIEN bit in the pin multiplexing control 0 register (PINMUX0) to 1. This enables
HPI/PCI functions on the EMIFA control and data pins and prevents the DSP from using the
EMIFA. DSP_BT is treated as 0 internally when BTMODE[3:0] = 001x, regardless of the
value at the configuration pin (the actual pin value should still be latched in the boot
configuration register (BOOTCFG) in the System Module).
SPRUEP9A – May 2008 Reset 119
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