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10.4.3 ARM Boot Mode Configuration
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The device configuration pins (BTMODE[3:0]) determine whether the ARM boots from its ROM or from the
asynchronous EMIF (EMIFA).
When ROM boot is selected (BTMODE[3:0] != 0100), a jump to the internal TCM ROM (0000 8000h) is
forced into the first fetched instruction word. The embedded ROM boot loader (RBL) code then performs
certain configuration steps, reads the boot configuration register (BOOTCFG) in the System Module to
determine the desired boot method, and branches to an appropriate secondary loader utility.
If EMIFA boot is selected (BTMODE[3:0] = 0100), a jump to the highest branch address (0200 0000h) is
forced into the first fetched instruction word. ARM Instruction Address Modification logic inserts a 1 on bit
30 of the address bus to modify the access to address 4200 0000h, which is the start of the EMIFA CS2
memory region. The ARM then continues executing from external memory using the default EMIFA
timings until modified by software. Code within the EMIFA memory should execute a branch to the actual
EMIFA address, and then disable the Instruction Address Modification logic by clearing the ADDRMOD bit
in the ARM boot configuration register (ARMBOOT) in the System Module.
Note: Either NOR Flash or ROM must be connected to the first EMIFA chip select space
(EM_CS2). The EMIFA does not support direct execution from NAND Flash.
The ARM boot configuration register (ARMBOOT) is used to control the ARM926 boot. The ARMBOOT
value does not change as a result of a global soft reset, instead the last value written is retained.
ARMBOOT is shown in Figure 10-2 and described in Table 10-4 . See device-specific data manual for
details on ARMBOOT.
Figure 10-2. ARM Boot Configuration Register (ARMBOOT)
31 16
Reserved
R-0
15 5 4 3 1 0
Reserved ADDRMOD Reserved TRAMBOOT
R-0 R/W-C R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; - n = value after reset
Table 10-4. ARM Boot Configuration Register (ARMBOOT) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reserved. Read returns 0.
4 ADDRMOD IAHB Address Modification. The default value for this bit is determined by the BOOTMODE
configuration bits (BTMODE[3:0]). If BTMODE[3:0] = 0100 [EMIFA direct boot (ROM/NOR)] , then
ADDRMOD defaults to 1 so that instruction fetches from the ARM point to EMIFA CS2 memory
space. For all other BTMODE[3:0] values, ADDRMOD defaults to 0 so the ARM boots from its TCM
(ROM or RAM).
0 No address modification.
1 Address bit 30 is tied high to modify IAHB fetch address to point to EMIFA.
3-1 Reserved 0 Reserved. Read returns 0.
0 TRAMBOOT ARM TCM RAM Boot. This is a "sticky" bit that can be used to force the ARM926 to boot from
ITCM RAM. On POR reset, this bit is initialized to 0 because TCM RAM is not initialized; otherwise,
the bit retains the value. After initializing ITCM RAM, software can set this bit so that subsequent
Warm reset ( RESET) or soft reset boots from the ITCM.
0 Use BTMODE[3:0] selected boot mode
1 Boot from ITCM RAM
SPRUEP9A – May 2008 Reset 117
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