User manual

9.5 Power Management
9.5.1 V
DD
3.3 V I/O Power-Down Control
9.6 Special Peripheral Status and Control
9.6.1 Universal Serial Bus (USB) Interface Control
9.6.2 Host Port Interface (HPI) Control
9.6.3 Video Clock Control and Disable
9.6.4 Transport Stream Interface (TSIF) Control
9.6.5 Video Source Clock Control and Disable
9.6.6 PWM Control
9.6.7 EDMA3 Transfer Controller (EDMA3TC) Burst Size Configuration
Power Management www.ti.com
The VDD 3.3V I/O power-down control register (VDD3P3V_PWDN) in the System Module controls power
to the 3.3 V I/O cells. The 3.3 V I/Os are separated into two groups for independent control. See the
device-specific data manual for details on VDD3P3V_PWDN.
Several of the DM646x DMSoC peripherals require additional system-level control logic. Those registers
are discussed in this section.
The USB control register (USBCTL) controls various features of the USB interface. See the device-specific
data manual for details on USBCTL.
The HPI control register (HPICTL) controls write access to the HPI control and address registers and
determines the host time-out value. HPICTL also determines the output mode of the HRDY signal.
HPICTL is not reset by a soft reset, so that the HPI width remains correctly configured. See the
device-specific data manual for details on HPICTL.
The video clock control register (VIDCLKCTL) allows you to select/control the clock multiplexing for the
video channel (channels 1, 2, and 3) output clock source. See the device-specific data manual for details
on VIDCLKCTL.
The TSIF control register (TSIFCTL) allows you to select/control the clock multiplexing for the counter and
serial output of TSIF1 and the counter and parallel/serial output for TSIF0. See the device-specific data
manual for details on TSIFCTL.
The video source clock disable register (VSCLKDIS) allows you to disable the selected video port
interface (VPIF), transport stream interface (TSIF), and clock reference generator (CRGEN) module input
clocks. See the device-specific data manual for details on VSCLKDIS.
Note: To ensure glitch-free operation, the clock should be disabled before changing the clock
source frequency or multiplexing using the video clock control register (VIDCLKCTL) and the
TSIF control register (TSIFCTL).
The PWM control register (PWMCTL) controls the chip-level connections of PWM0 and PWM1. See
device-specific data manual for details on PWMCTL.
The EDMA transfer controller default burst size configuration register (EDMATCCFG) configures the
default burst size (DBS) for the EDMA transfer controllers (EDMA3TC0, EDMA3TC1, EDMA3TC2, and
EDMA3TC3). See the device-specific data manual for details on EDMATCCFG.
System Control Module106 SPRUEP9A – May 2008
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