User manual

8.4.17 Interrupt Priority Register 6 (INTPRI6)
8.4.18 Interrupt Priority Register 7 (INTPRI7)
www.ti.com AINTC Registers
The interrupt priority register 6 (INTPRI6) is shown in Figure 8-21 and described in Table 8-19 .
Figure 8-21. Interrupt Priority Register 6 (INTPRI6)
31 30 28 27 26 24 23 22 20 19 18 16
Reserved INT55 Reserved INT54 Reserved INT53 Reserved INT52
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
15 14 12 11 10 8 7 6 4 3 2 0
Reserved INT51 Reserved INT50 Reserved INT49 Reserved INT48
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-19. Interrupt Priority Register 6 (INTPRI6) Field Descriptions
Bit Field Value Description
Reserved 0 Reserved
INT n 0-7h Selects INT n priority level.
The interrupt priority register 7 (INTPRI7) is shown in Figure 8-22 and described in Table 8-20 .
Figure 8-22. Interrupt Priority Register 7 (INTPRI7)
31 30 28 27 26 24 23 22 20 19 18 16
Reserved INT63 Reserved INT62 Reserved INT61 Reserved INT60
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
15 14 12 11 10 8 7 6 4 3 2 0
Reserved INT59 Reserved INT58 Reserved INT57 Reserved INT56
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-20. Interrupt Priority Register 7 (INTPRI7) Field Descriptions
Bit Field Value Description
Reserved 0 Reserved
INT n 0-7h Selects INT n priority level.
SPRUEP9A – May 2008 ARM Interrupt Controller (AINTC) 101
Submit Documentation Feedback