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8.4.15 Interrupt Priority Register 4 (INTPRI4)
8.4.16 Interrupt Priority Register 5 (INTPRI5)
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The interrupt priority register 4 (INTPRI4) is shown in Figure 8-19 and described in Table 8-17 .
Figure 8-19. Interrupt Priority Register 4 (INTPRI4)
31 30 28 27 26 24 23 22 20 19 18 16
Reserved INT39 Reserved INT38 Reserved INT37 Reserved INT36
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
15 14 12 11 10 8 7 6 4 3 2 0
Reserved INT35 Reserved INT34 Reserved INT33 Reserved INT32
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-17. Interrupt Priority Register 4 (INTPRI4) Field Descriptions
Bit Field Value Description
Reserved 0 Reserved
INT n 0-7h Selects INT n priority level.
The interrupt priority register 5 (INTPRI5) is shown in Figure 8-20 and described in Table 8-18 .
Figure 8-20. Interrupt Priority Register 5 (INTPRI5)
31 30 28 27 26 24 23 22 20 19 18 16
Reserved INT47 Reserved INT46 Reserved INT45 Reserved INT44
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
15 14 12 11 10 8 7 6 4 3 2 0
Reserved INT43 Reserved INT42 Reserved INT41 Reserved INT40
R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h R-0 R/W-7h
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 8-18. Interrupt Priority Register 5 (INTPRI5) Field Descriptions
Bit Field Value Description
Reserved 0 Reserved
INT n 0-7h Selects INT n priority level.
ARM Interrupt Controller (AINTC)100 SPRUEP9A – May 2008
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