Datasheet

To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13
SN74LVCH16T245-EP
SCES726A –NOVEMBER 2008 –REVISED NOVEMBER 2013 www.ti.com
DESCRIPTION (CONTINUED)
The SN74LVCH16T245 is designed for asynchronous communication between two data buses. The logic levels
of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-
port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus
to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level
applied to prevent excess I
CC
and I
CCZ
.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, then all outputs are in the high-impedance
state. The bus-hold circuitry on the powered-up side always stays active.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Table 1. ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
TVSOP – DGV Tape and reel CLVCH16T245MDGVREP LDHT245MEP
–50°C to 125°C
TSSOP - DGG Tape and reel CLVCH16T245MDGGREP 8UT245MEP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(1)
(EACH 16-BIT SECTION)
CONTROL INPUTS OUTPUT CIRCUITS
OPERATION
OE DIR A PORT B PORT
L L Enabled Hi-Z B data to A bus
L H Hi-Z Enabled A data to B bus
H X Hi-Z Hi-Z Isolation
(1) Input circuits of the data I/Os are always active.
LOGIC DIAGRAM (POSITIVE LOGIC)
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