Datasheet

V
EE
V
CC
V
EE
V
CC
CLC007
8
4
3
5
2
R8
75:
C3
0.1 PF
R7
75:
C2
0.1 PF
J4
V
CC
6
7
J5
J2
V
IN+
R1
154:
R4
75:
V
EE
R3
154:
R5
75:
J1
V
IN-
-
+
R6
75:
C1
0.1 PF
J3
R9
75:
C4
0.1 PF
J6
1
CLC007
SNLS016E –JULY 1998–REVISED APRIL 2013 www.ti.com
Figure 7. Differential 50Ω ECL Input
Output Interfacing
The CLC007’s class AB output stage, Figure 8, requires no standing current in the output transistors and
therefore requires no biasing or pull-down resistors. Advantages of this arrangement are lower power dissipation
and fewer external components. The output may be either D.C. or A.C. coupled to the load. A bandgap voltage
reference sets output voltage levels which are compatible with F100K and 10K ECL when correctly terminated.
The outputs do not have the same output voltage temperature coefficient as 10K. Therefore, noise margins will
be reduced over the full temperature range when driving 10K ECL. Noise margins will not be affected when
interfacing to F100K since F100K is fully voltage and temperature compensated.
Figure 8. Output Stage
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