Datasheet

CLC007
8
1
2
5
3
V
CC
6
7
R2
R1
R2
R1
-
+
0.1 PF
0.1 PF
V
EE
V
CC
V
EE
Z
0
Z
0
V
TT
V
TT
ECL Output
4
To next
stage
V
IN+
V
IN-
V
EE
V
CC
CLC007
SNLS016E –JULY 1998–REVISED APRIL 2013 www.ti.com
OPERATION
Input Interfacing
The CLC007 has high impedance, emitter-follower buffered, differential inputs. Single-ended signals may also be
input. Transmission lines supplying input signals must be properly terminated close to the CLC007. Either A.C. or
D.C. coupling as in Figure 4 or Figure 5 may be used. Figure 4, Figure 6, and Figure 7 show how Thevenin-
equivalent resistor networks are used to provide input termination and biasing. The input D.C. common-mode
voltage range is 0.8V to 2.5V below the positive power supply (V
CC
). Input signals plus bias should be kept within
the specified common-mode range. For an 800 mV
P-P
input signal, typical input bias levels range from 1.2V to
2.1V below the positive supply.
Load Type Resistor to V
CC
(R1) Resistor to V
EE
(R2)
ECL, 50Ω, 5V, V
T
=2V 82.5Ω 124Ω
ECL, 50Ω, 5.2V, V
T
=2V 80.6Ω 133Ω
ECL, 75Ω, 5V, V
T
=2V 124Ω 187Ω
ECL, 75Ω, 5.2V, V
T
=2V 121Ω 196Ω
800 mV
P-P
, 50Ω, 5V, V
T
=1.6V 75.0Ω 154Ω
800 mV
P-P
, 75Ω, 5V, V
T
=1.6V 110Ω 232Ω
800 mV
P-P
, 2.2 KΩ, 5V, V
T
=1.6V 3240Ω 6810Ω
Figure 3. Input Stage
Figure 4. AC Coupled Input
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