Datasheet

Configuring the Board

www.ti.com

Input Buffer Selection Pin (ITTP): The TERM pin will select the input buffer type of both IN1 and IN2

inputs. The header ITTP (JP_3_22) is dedicated for this pin.

Table 5. Input Buffer Settings

Jumper on ITTP Header Output Type

GND LVDS

VDD HCSL

OPEN LVCMOS

The LVDS differential buffers have external biasing and termination on the EVM. JMP7 and JMP8 should

be configured based on the type of input selected (1.2V for LVDS, 0.9V for 1.8V LVDS, 0V for HCSL). For

HCSL and LVCMOS dc coupled input should be used.

Smart Input Multiplexer Control pin (INSEL): The INSEL pin will select the input clock for buffering. The

header INSEL (JP_3_21) is dedicated for this pin.

Table 6. Smart Mux Settings

Jumper on INSEL Header IN1 Buffer Setting IN2 Buffer setting

GND ON and selected by INSEL Multiplexer OFF

VDD OFF ON and selected by INSEL Mux

OPEN Smart Multiplexer selects input. IN1 is the primary input (it has the highest priority, therefore if it

is available, the smart multiplexer selects IN1)

Configuring the Outputs

All eight differential outputs are connected to SMA through ac-coupling. Outputs are connected 50 Ω to

GND through Headers. Each Header pin has an option of capacitor connected to ground (not populated).

Each output also has option of series termination resistor ( 0 Ω populated) for LVCMOS and HCSL if

needed.

The EVM output settings must be configured accordingly to generate the proper formats.

HCSL Outputs – Place the jumpers in the Headers (J14/J15/J20/J21) and place series resistors

if needed

LVDS Outputs – Do not use jumpers on the Headers (J14/J15/J20/J21)

LVCMOS Outputs – Remove all 50 Ω

CDCUN1208LP Evaluation Board SCAU050–May 2012

Submit Documentation Feedback