Datasheet

Hardware Configuration
3-4
3.2.4 Loop Filter (J32−J34)
The loop filter is one of the key elements determining the loop bandwidth of
the PLL. The loop filter converts the charge pump current into the control
voltage for the voltage controlled oscillator. The phase difference between the
input clocks of the phase frequency detector determines the width of the
charge pump output current pulses. These high frequency pulses are
transformed into a voltage to control the oscillator.
Basically, three types of loop filters are implemented on the EVM.
- Passive loop filter
- External active loop filter using an external low-noise OPA.
Filter types can be selected by soldering bridges J32−J34, see Table 3−1.
Control voltage of the VC(X)O can be measured at J9 or TP1. If an external
OPA is used, it needs to be switched on by connecting J34. For example,
passive filter operation is provided when pads 1 and 3 of J33 are solder bridged
and pads 1 and 3 of J32 are solder bridged.
Default setting: Passive Loop Filter
Table 3−1.Filter Configurations
Bridge Passive Filter Active With An External OPA
J33 1−3 1−2
J34 Open Closed
J32 1−3 1−2
3.2.5 High-Speed Outputs and Inputs (J1−J4, J6−J11, J13, J14, J22, and J23)
The CDCM7005 drives five differential LVPECL outputs. All PECL outputs are
ac-coupled and terminated with 150 Ω to GND. This is in contrast to typical
LVPECL termination, which requires V
CC
− 2 V as termination voltage. The
reason is to simplify the power supply scheme. The device output’s trace
impedance is 50 Ω and traces are matched in length. All outputs have options
for pullup and pulldown resistors.
When the CDCM7005 is powered up, it defaults to five LVPECL outputs.
However, this EVM is configured as follows:
- Y0 − Y2 = LVPECL
- Y3, Y4 = LVCMOS (in addition Y4 has an option for a custom filter)
The reference input clock signal has to be applied to J1 or J6. The reference
input clock signal can be sensed on J4. In this case, close the bridge J5 (the
oscilloscope’s 50 Ω may be used to terminate the 50-Ω trace). The reference
input clock sense line is matched to the LVPECL outputs line to avoid any
additional delay offset. The input is ac-coupled (C4).
3.2.6 VC(X)O Inputs and Outputs (J16−J18)
The CDCM7005 requires an external VC(X)O in order to complete the PLL
loop. The VC(X)O adjusts the frequency and phase depending on the control
voltage level coming from the loop filter and provide the input clock to the
LVPECL block.
Another option would be to use an external source via J16 and J18.