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2005 Clock Drivers

User’s Guide

SCAU013A

Summary of content (35 pages)

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!! " User’s Guide 2005 Clock Drivers SCAU013A
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
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EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the supply voltage range of 3 V and 3.6 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
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Related Documentation From Texas Instruments Preface About This Manual This manual explains how to use the CDCM7005 evaluation module (EVM) and provides guidelines to build the customer’s own systems. The manual includes schematics, layout, bill of materials, and a software description.
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Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 CDCM7005 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 2 Quick Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3 EVM Hardware . . . . . . . . . . . . . . . . . . .
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Contents 3−1 4−1 5−1 5−2 6−1 6−2 6−3 6−4 6−5 6−6 Board View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Screen View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 CDCM7005 With a Passive Loop Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes an on-board voltage controlled crystal oscillator (VC(X)O) frequency to an external reference clock. The device operates up to 1.3 GHz. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements by selecting the external VC(X)O, loop filter components, frequency for PFD, and charge pump current.
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CDCM7005 Functional Block Diagram 1.1 CDCM7005 Functional Block Diagram AVCC VCC VCC_CP Selected REF Signal REF_SEL Manual & Automatic CLK Select STATUS_REF / PRI_SEC_CLK STATUS_VCXO / I_REF_CP freq. detect > 2 MHz PLL_LOCK PRI_REF LVCMOS SEC_REF REF_MUX freq. detect > 2 MHz Reference Clock Feedback Clock Progr. Delay M Progr. Divider M 210 Progr. Delay N Progr.
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Chapter 2 In order to setup the EVM quickly and to take some measurements at default settings, the following actions are required: - Supply 3.3 V to P1, LED D4 will be on. - Apply a single-ended reference clock to the reference clock input PRI_REF (pin A1) or SEC_REF (pin B1). For default setting, the reference clock must be 1/8th of the VC(X)O frequency. If REF_SEL is set to 1, then PRI_REF is selected. If REF_SEL is set to 0, then SEC_REF is selected.
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Chapter 3 This chapter discusses the EVM hardware. Topic Page 3.1 Board View and Connector Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Board View and Connector Location 3.1 Board View and Connector Location Figure 3−1.
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Hardware Configuration 3.2 Hardware Configuration This section describes the board configuration using on-board jumpers and solder bridges. 3.2.1 Power Supply (P1, P2) - Supply 3.3 V ±10% on P1 and P2 using a stabilized external power supply. J 3.2.2 WARNING: Never supply more than 3.6 V on P1. Onboard Switches and Indicators (SW1−SW2, D1−D4) - Push SW1 to enter the power-down mode of the CDCM7005 device.
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Hardware Configuration 3.2.4 Loop Filter (J32−J34) The loop filter is one of the key elements determining the loop bandwidth of the PLL. The loop filter converts the charge pump current into the control voltage for the voltage controlled oscillator. The phase difference between the input clocks of the phase frequency detector determines the width of the charge pump output current pulses. These high frequency pulses are transformed into a voltage to control the oscillator.
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Hardware Configuration 3.2.7 AC-Coupling at PRI_REF (C1, R4, R6) and SEC_REF (C5, R13, R15) An ac-coupling is provided at PRI_REF and SEC_REF to ease the use of the CDCM7005 with different signaling levels (LVCMOS, LVPECL, LVDS,...). However, the ac-coupling will increase the PLL stabilization time after power up due to transient effects. It also increases the switching time between PRI_REF and SEC_REF in case of automatic reference clock switching.
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Chapter 4 ! " # ! "$# This chapter discusses the serial peripheral interface software. Topic Page 4.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 1) Copyright 2005 National Instruments Corporation. All Rights Reserved. Copyright 2005 Texas Instruments Incorporated. All Rights Reserved.
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Functional Description 4.1 Functional Description Programming software here as described is intended for programming the internal control register of the CDCM7005. The software runs under Windows 2000 / XP / XP *64. A quick installation is required prior to use. See the Software Installation section. There are several cases where programming is mandatory.
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Chapter 5 % & ' This chapter discusses the application circuit diagram. Topic 5.1 Page Application Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Application Circuit Diagram 5.1 Application Circuit Diagram The following applications sections the two loop filter configurations are discussed. 5.1.1 Passive Loop Filter The passive loop filter is a second order filter (two poles, one zero). The zero is required for the overall loop stability. R1, C1, and C2 generate the dominant pole of the system. A second pole is introduced by R2 and C3. Figure 5−1. CDCM7005 With a Passive Loop Filter Configuration Low-Pass Filter R2 160 Ω VC(X)O 491.
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Application Circuit Diagram 5.1.2 External Active Loop Filter Using OPA341 Figure 5−2. CDCM7005 With a External Active Loop Filter Using OPA341 Low-Pass Filter R3 10 kΩ VC(X)O 491.52 MHz PECL_OUT_B PECL_OUT V_CTRL C3 100 nF Vcc R2 4.
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Chapter 6 ( ) * ( + ) ' This chapter contains the parts list, board layout, and schematic for the CDCM7005 EVM. Topic Page 6.1 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Parts List 6.1 Parts List Item QTY Reference Designator C1−C9, C12, C13, C15, C17, C26, C40, C41, C46, C47, C53, C54, C56−C58, C66 C72, C10 Footprint Part smd_cap_0402 10 nF Panasonic ECJ−0EB1E103K smd_cap_0402 100 nF smd_cap_0402 100 pF Panasonic ECJ−0EB1E104K Panasonic ECJ−0EB1E101K smd_cap_0402 0Ω 1 24 2 2 3 7 4 2 C11, C32, C62−C64, C68, C73 C14, C16 5 1 C18 smd_cap_0402 1000 pF 6 1 C19 smd_cap_0603 1 µF 7 2 C20, C22 smd_cap_0402 0.
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Parts List Item QTY 22 2 Reference Designator Footprint Part Part Number C74 smd_cap_1210 10 µF Murata GRM32DR61E106KA12L C77 smd_cap_1210 10 µF Murata GRM32DR61E106KA12L 23 1 C78 smd_cap_0805 NU Panasonic ECP−U1C104MA5 24 25 3 1 D1−D3 D4 smd_led_1206 smd_led_1206 Amber GREEN Lite−On LTST−C150AKT Lite−On LTST−C150KGKT 26 27 1 7 FLT1 J1−J4, J6−J8 ts−38s sma_alt TS−38S SMA Toyocom Filter Johnson Comp 142−0701−841 28 1 J5 jumper2 HEADER 2 29 9 sma_alt NU_SMA 30 4 J9−J
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Parts List Item QTY Reference Designator R4, R6, R13, R15, R62, R63, R65 R5, R8, R14, R17, R21, R23 R25, R57, R59, R60, R68−R71, R74, R75 R28, R45 Footprint Part smd_res_0402 100 Ω smd_res_0402 150 Ω smd_res_0402 10 kΩ smd_res_0402 NU 0 Ω R29, R32, R49, R80 R38, R31 smd_res_0402 NU 150 Ω smd_res_0402 130 Ω smd_res_0402 0Ω smd_res_0402 82 Ω 48 7 49 6 50 10 51 2 52 4 53 2 54 10 55 2 R33, R34, R41, R42, R82,−R87 R43, R36 56 57 2 2 R37, R44 R39, R40 smd_res_0402 smd_res_
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Parts List 6.2 Board Layout Figure 6−1.
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Parts List Figure 6−2.
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Parts List Figure 6−3.
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Parts List Figure 6−4.
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Parts List Figure 6−5.
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Parts List Figure 6−6. Power Layer View 6.3 Schematic The following pages contain the schematic for the CDCM7005.
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A B C 5 1 1 GND P2 1 1 PW R_IN P1 R61 1.
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A B C D GND 5 GND RST C35 1 C34 GND 1 2 J26 3 1 PRI_REF SEC_REF GND 2 10n 10n R60 10K 2 1 4 B2 B3 B4 B5 H1 H8 D1 E1 A1 B1 A2 A5 A6 A7 C7 C6 C5 C4 C3 A3 AVCC REF_SEL CTRL_LE CTRL_CLK CTRL_DATA R59 10K VCXO_INB P W RDW N 2 1 VCXO_IN 1 PW R_ DW N 2 J28 RESET 1 2 2 1 2 J29 GND GND SW2 SW1 VCC VCC_CP 1 2 C32100P C3122n 1 2 4 VCC D7 E3 E4 E5 E6 E7 E8 F7 G2 G3 G4 VCC G5 VCC G6 VCC G7 CP_OUT A4 PLL_LOCKA8 PRI_REF VBB C1 SEC_REFSTATUS_REFC8 REF_SEL STATUS_VCXOD8 CTRL_LE Y0 F1 CT
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A B C 5 GND .1uF C27 2 1 V_CTRL R51 2 100K V CHECK J24 1 V_CTRL 2 1 3 R52 2 160 4 C28 .1uF 1 C29 .1uF J32 GND C30 22uF R53 4.7K R70 2 10K GND .1uF C76 1 GND 3 .1uF C79 2 1 C77 2 1 1 R72 2 4.7K 10uF C78 2 1 NU J33 R73 180 R71 10K 2 1 C74 10uF C75 .1uF 6 OPA341 GND 2 1 4 2 1 2 1 5 7 − 2 + 3 CP_OUT U5 GND L8 2.
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A B C D Y4B Y3B Y2B Y1B R80 NU 150 Y4 Y3 Y2 J20 1 R49 NU 150 GND 5 R8 150 GND 1 R84 2 0 ohm 10n 2 VCC 1 GND 2 R40 ** 62 1 NU 100 R50 2 NU 100 R48 SMA J8 2 R24 NU 100 R35 NU 100 2 2 FLT1 1 IN J19 ** 75 ohm@100MHz 1 2 L1 C19 ** 1uF GND 4 2 NU_SMA J23 GND 2 2 L4 ** 180nH GND VCC 2 1 GND C25 ** NU 1pF ** 22pFC24 2 GND SMA J3 NU_SMA J13 GND NU_SMA J14 GND GND 1 R27 NU 100 1 NU_SMA J11 GND VCC Y2B_SMA 1 2 SMA J7 1 3 NU_SMA J10 GND 1 GND GND Y1
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A B C 5 4 C 70 1 1 R63 100 10p GND SPI_DATA SPI_CLK SPI_LE 2 2 1 2 R62 100 10p C 71 1 2 C 69 10p 1 2 1 J31 2 3 4 HDR4 GND 4 1 1 2 3 4 5 6 7 8 9 10 11 12 13 2 GND 3 VCC 3 10KR69 1 2 VCC 14 R 68 10K 132 1 12 11 10 GND 9 DATA 8 VCC 1OE VCC 1A 4OE 4A 1Y 2OE 4Y 2A 3OE 2Y 3A GND 3Y SN74LV125U3 1 2 C73100P C72100n 1 2 14 J30 15 16 17 18 19 20 21 22 23 24 25 26 27 1 2 3 4 5 6 7 VCC R 67 100K 1 R 66 100K 1 GND 2 R64 100K 1 GND CLK LE R65 100 2 CTRL_LE CTRL_CLK CTRL_DAT