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Configuring the Board

6.12 Output Signal Type Selection

Outputs Y0–Y3 offer LP-CML (LVDS like), CML or HS-CML (LVPECL like) signaling types. Using the pull-

down menu, one of the signal types is selected for each output or can disable the output channel

completely. Outputs Y4–Y7 offer LP-CML (LVDS like), HCSL or LVCMOS signaling types. Using the pull-

down menu, one of the signal types is selected for each output or can disable the output channel

completely. If the LVCMOS signal type is selected, check Enable boxes, enabling the outputs individually.

6.13 Additional Features

The EVM software GUI comes with tools that are helpful in optimizing the device settings for best

performance. These include a Frequency Planning Tool, the Loop Filter Simulator, and the Phase-Noise

Simulator. Each of these tools are described in detail in the Help documentation provided in the GUI.

7 Configuring the Board

The CDCM6208 is a programmable clock driver with many options. The EVM was designed with

maximum flexibility so engineers can configure the EVM for operation at its desired mode.

7.1 Selecting the Interface Connection

The CDCM6208 is configurable via the serial interface or control pins. Both SPI and I

C interface options

are available for configuring the device. Switch SW1 is dedicated for the SPI interface and switch SW2 is

for the I

C interface. The selected interface switch must be turned on and the other switch must be turned

off. Both switches must be turned off for Pin control mode.

Header JMP9 also connects an external host to SPI or I

7.2 Configuring the Power Supply

The device is powered up with an external power supply or on-board regulators powered by an attached

USB cable. The EVM has options for 1.8-, 2.5-, and 3.3-V power supplies. These supply voltages are

external to, or internal from the regulators. It has five different rails – two for outputs, one for PLL, one for

digital logic, and one for reference input power supplies.

The banana jacks (P2, P3, and P4) are external 3.3 V, 2.5 V, and 1.8 V, respectively. Banana jack P1 is

for GND. Low-dropout regulators U6, U7, and U8, generate 3.3 V, 2.5 V, and 1.8 V, respectively. The

jumper on header JP_3_10 selects between an external or internal 3.3 V, the jumper on header JP_3_11

selects between an external or internal 2.5 V, and the jumper on header JP_3_12 selects between an

external or internal 1.8 V.

The jumpers on the header JMP5 select for the DVDD power rail, JMP1 selects for the PLL power rails,

JMP3 selects for the output power rails (Y2, Y3, Y6, and Y7), JPM2 selects for the output power rails (Y0,

Y1, Y4, and Y5) and JPM4 selects for the reference input power rails from 3.3-, 2.5-, and 1.8-V power

supplies. Mixed power supplies for this device are possible, using these headers.

NOTE: A USB cable must be connected for biasing voltage generation of 1.2 V and 0.9 V for the

reference inputs. These biasing voltages are generated by the on-board regulators which rely

on the USB supply. Figure 3 shows the jumper configuration for a USB power supply. The

EVM settings drive the device from the USB with 1.8-V and 3.3-V supplies. Jumpers for the

header JP_3_10 are set to 3.3-V regulator and for JP_3_3_12 header to 1.8-V regulator.

DVDD (JMP5), VDD_PLL (JMP1), VDD_IN (JMP4), and VDD_OUTB (JMP3) supplies are

set to 1.8 V and VDD_OUTA (JMP2) supply is set to 3.3 V. The entire device is running at

1.8 V, except the Y0, Y1, Y4, and Y5 outputs which are running at 3.3 V.

SCAU049A–May 2012–Revised January 2013 CDCM6208 Evaluation Board

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