Datasheet

OUTP1
OUTN1
OUTP0
OUTN0
OUTP2
OUTN2
OUTP7
OUTN7
OUTP5
OUTN5
OUTP4
OUTN4
OUTP6
OUTN6
OUTP3
OUTN3
1 2
R80 150R80 150
1
JP20JP20
1 2
R102150R102150
1
JP9JP9
2 3
1
4 5
J17
SMA-EDGE
J17
SMA-EDGE
2 3
1
4 5
J13
SMA-EDGE
J13
SMA-EDGE
1 2
R84 150R84 150
1
2
R63
150
R63
150
1
JP21JP21 C46
0.1uF
C46
0.1uF
1 2
R82 150R82 150
1 2
R81 150R81 150
1
JP10JP10
1 2
R88 150R88 150
1 2
R85 150R85 150
1
2
R64
150
R64
150
2 3
1
4 5
J27
SMA-EDGE
J27
SMA-EDGE
C47
0.1uF
C47
0.1uF
1
JP22JP22
1 2
R86 150R86 150
1 2
R83 150R83 150
1 2
R89 150R89 150
1
JP11JP11
1
2
R59
150
R59
150
1
JP25JP25
C61
0.1uF
C61
0.1uF
1 2
R87 150R87 150
1
JP23JP23
2 3
1
4 5
J23
SMA-EDGE
J23
SMA-EDGE
1
JP26JP26
1
JP12JP12
1
2
R61
150
R61
150
1
JP24JP24
C62
0.1uF
C62
0.1uF
1 2
R101 150R101 150
1
JP8JP8
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Figure 3. CDCLVP1216EVM—Schematic
SCAU029 – May 2009 Low Additive Phase Noise Clock Buffer Evaluation Board 5
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