Datasheet

5 Output Clock
6 Schematics and Layout
www.ti.com Output Clock
The CDCLVP1216 generates up to 16 LVPECL outputs. Four outputs are available on the
CDCLVP1216EVM (outputs 0, 7, 8, and 15) through the following SMAs:
• J13, J23 for OUT0
• J17, J27 for OUT7
• J33, J32 for OUT8
• J39, J38 for OUT15
The LVPECL outputs are terminated with 150 Ω to ground and ac-coupled to the respective SMAs.
Figure 2 through Figure 4 show the printed circuit board (PCB) schematics.
Note: Board layouts are not to scale. These figures are intended to show how the board is laid out;
they are not intended to be used for manufacturing CDCLVP1216EVM PCBs.
SCAU029 – May 2009 Low Additive Phase Noise Clock Buffer Evaluation Board 3
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