Datasheet

1 General Description
2 Signal Path and Control Circuitry
3 Getting Started
3.1 Power-Supply Connections
4 Input Clock Selection
4.1 Configuring Single-ended Input
General Description www.ti.com
The CDCLVP1216 is a high-performance, low additive phase noise clock buffer. It has two universal input
buffers that support either single-ended or differential clock inputs, selectable through a control pin. The
device also features on-chip bias generators that can provide the LVPECL common-mode voltage to the
device inputs.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP1216.
This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP1216
device functionalities. Throughout this document, the acronym EVM and the phrases evaluation module
and evaluation board are synonymous with the CDCLVP1216EVM. See Figure 1 for an illustration of the
CDCLVP1216EVM.
For optimum performance, the board is equipped with 50- Ω SMA connectors and well-controlled, 50- Ω
impedance microstrip transmission lines.
The CDCLVP1216 supports single-ended inputs up to 200 MHz and differential inputs up to 2 GHz. The
device provides up to 16 LVPECL outputs operating at the input frequency. For more information about
the CDCLVP1216, see the CDCLVP1216 product data sheet available for download from the TI web site
(www.ti.com ).
The CDCLVP1216EVM has self-explanatory labeling and uses similar naming conventions as the
CDCLVP1216 product data sheet. In this user's guide, all words in boldface and italic print reflect the
actual labeling on the EVM. The CDCLVP1216EVM can be used with either single-ended or differential
inputs.
Connect the power-supply source to the banana plug labeled VDD (P4), and connect the ground of the
power-supply source to GND (P5). There are decoupling capacitors and ferrite bead to isolate the EVM
power from the CDCLVP1216 device power pins.
The CDCLVP1216EVM can use a supply voltage of 2.375 V to 3.6 V.
The CDCLVP1216EVM offers users the option of receiving either a differential or single-ended clock as
the clock input. The default option is for the differential signal at both device inputs. The inputs can be
applied through the SMAs (J103, J104 or J105, J106). These inputs are ac-coupled to the device inputs.
The common-mode voltage for these inputs after the ac-coupling capacitors are provided by 50 Ω (R152,
R153 and R154, R155) to the device on-chip bias generator (V
AC_REF
) pins. Either of the two input clocks
can be selected using jumper JP1. When JP1 is shorted, IN0 is selected. When JP1 is open, IN1 is
selected.
For a single-ended clock applied to IN0, remove capacitors C68 and C69 and replace them with 0- Ω
resistors of the same footprint. The single-ended signal should be applied to INP0 (J103) and the dc bias
voltage should be applied to INN0 (J104).
For a single-ended clock applied to IN1, remove capacitors C72 and C73 and replace them with 0- Ω
resistors of the same footprint. The single-ended signal should be applied to INP1 (J105) and the dc bias
voltage should be applied to INN1 (J106).
Low Additive Phase Noise Clock Buffer Evaluation Board2 SCAU029 – May 2009
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