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Output Clock

5 Output Clock

The CDCLVP1208 generates up to eight LVPECL outputs. Four outputs are available on the

CDCLVP1208EVM (outputs 0, 3, 4, and 7) through the following SMAs:

• J13, J23 for OUT0

• J17, J27 for OUT3

• J33, J32 for OUT4

• J39, J38 for OUT7

The LVPECL outputs are terminated with 150 Ω to ground and ac-coupled to the respective SMAs.

6 Schematics and Layout

Figure 2 and Figure 3 show the printed circuit board (PCB) schematics.

NOTE: Board layouts are not to scale. These figures are intended to show how the board is laid

out; they are not intended to be used for manufacturing CDCLVP1208EVM PCBs.

Figure 2. CDCLVP1208EVM—Schematic

SCAU038–October 2009 Low Additive Phase Noise Clock Buffer Evaluation Board

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