Datasheet

OUTP1
OUTN1
OUTP0
OUTN0
OUTP3
OUTN3
OUTP2
OUTN2
C107
0.1uF
C107
0.1uF
1 2
R80 150R80 150
1
JP20JP20
1
JP21JP21
1
JP9JP9
2 3
1
4 5
J13
SMA-EDGE
J13
SMA-EDGE
2 3
1
4 5
J39
SMA-EDGE
J39
SMA-EDGE
C46
0.1uF
C46
0.1uF
1 2
R82 150R82 150
1 2
R81 150R81 150
1
2
R108
150
R108
150
C47
0.1uF
C47
0.1uF
2 3
1
4 5
J38
SMA-EDGE
J38
SMA-EDGE
1
2
R59
150
R59
150
1 2
R83 150R83 150
1
2
R109
150
R109
150
2 3
1
4 5
J23
SMA-EDGE
J23
SMA-EDGE
1
2
R61
150
R61
150
C106
0.1uF
C106
0.1uF
1
JP8JP8
www.ti.com Schematics and Layout
Figure 3. CDCLVP1204EVM—Schematic
SCAU032 – July 2009 Low Additive Phase Noise Clock Buffer Evaluation Board 5
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