Datasheet

1 General Description
2 Signal Path and Control Circuitry
3 Getting Started
3.1 Power-Supply Connections
General Description www.ti.com
The CDCLVP1204 is a high-performance, low additive phase noise clock buffer. It has two universal input
buffers that support either single-ended or differential clock inputs, selectable by a control pin. The device
also features on-chip bias generators that can provide the LVPECL common-mode voltage to the device
inputs.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP1204.
This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP1204
device functionalities. Throughout this document, the acronym EVM and the phrases evaluation module
and evaluation board are synonymous with the CDCLVP1204EVM. Figure 1 illustrates the
CDCLVP1204EVM.
For optimum performance, the board is equipped with 50- Ω SMA connectors and well-controlled, 50- Ω
impedance microstrip transmission lines.
The CDCLVP1204 supports single-ended inputs up to 200 MHz and differential inputs up to 2 GHz. The
device provides up to four LVPECL outputs operating at the input frequency. For more information about
the CDCLVP1204, see the CDCLVP1204 product data sheet available for download from the TI web site
(www.ti.com ).
The CDCLVP1204EVM has self-explanatory labeling and uses similar naming conventions as the
CDCLVP1204 product data sheet. In this user's guide, all words in boldface and italic print reflect the
actual labeling on the EVM. The CDCLVP1204EVM can be used with either single-ended or differential
inputs.
Connect the power-supply source to the banana plug labeled VDD (P4), and connect the ground of the
power-supply source to GND (P5). There are decoupling capacitors and a ferrite bead to isolate the EVM
power from the CDCLVP1204 device power pins.
The CDCLVP1204EVM can use a supply voltage of 2.375 V to 3.6 V.
Low Additive Phase Noise Clock Buffer Evaluation Board2 SCAU032 – July 2009
Submit Documentation Feedback