Datasheet

General Description

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2 General Description

The CDCLVD1212 and CDCLVD2106 are high performance low additive phase noise clock buffers. The

devices have two universal input buffers, that supports single ended or differential clock inputs, and

selectable through a control pin (for CDCLVD1212 only). The devices also feature on-chip bias generators

that can provide the LVDS common mode voltage to the device inputs.

The Evaluation Module (EVM) is designed to demonstrate the electrical performance of the CDCLVD1212

or CDCLVD2106. This fully assembled and factory tested evaluation board allows complete validation of

device functionalities. For optimum performance, the board is equipped with SMA connectors and

well-controlled 50Ω impedance micro strip transmission lines.

3 Signal Path and Control Circuitry

The CDCLVD1212 and CDCLVD2106 support single ended inputs up to 200MHz and differential inputs up

to 800MHz. Each device provides up to 12 LVDS outputs operating at the input frequency or frequencies.

For more information, see the CDCLVD1212 or CDCLVD2106 product data sheet for details.

4 Getting Started

The EVM has self-explanatory labeling and offers almost same naming convention as used in the data

sheet. All words in bold and italics print in this document is the actual labeling on the EVM. The EVM can

be used with single ended or differential inputs.

5 Device Selection

Same EVM is used for both CDCLVD1212 (2:12 single buffer) and CDCLVD2106 (1:6 dual buffer). The

assembled product is highlighted with a marker in front of the silkscreen.

6 Power Supply Connection

Connect the power supply source to banana plug labeled VDD (P1) and connect the ground of the power

supply source to the GND (P2). There are decoupling capacitors and ferrite bead to isolate the EVM

power from the device’s power pins.

2.375 – 2.625V supply voltage can be used in this EVM.

7 Input Clock Selection

The CDCLVD1212and CDCLVD2106EVM offer options of receiving either differential or single ended

clock as clock input. The default option is for the differential signal at both device inputs. The inputs can

be applied through the SMAs, J1, J2 and J3, J4. These inputs are ac coupled to the device inputs and the

common mode voltage for these inputs after the ac coupling capacitors are provided by 50Ω (R2, R3 and

R5, R6) to the device on-chip bias generator (V

AC_REF

) pins.

CDCLVD1212: Either of the 2 input clocks can be selected using the jumper JPM1. When pin 2 of JPM1

jumper is connected to GND, IN0 is selected and connected to VDD, IN1 is selected. The jumper must be

used in JPM1, otherwise all ouptuts and inputs will be disabled.

7.1 Configuring Single-Ended Input

For single ended clock applied to IN0, remove the capacitors C1 and C2 and replace them with 0Ω

resistors of the same footprint and also remove R2 and R3 the biasing resistors. The single ended signal

should be applied to INP0 (J2) and the DC bias voltage should be applied to INN0 (J1).

For single ended clock applied to IN1, remove the capacitors C3 and C4 and replace them with 0Ω

resistors of the same footprint and also remove R5 and R6 the biasing resistors. The single ended signal

should be applied to INP1 (J3) and the DC bias voltage should be applied to INN1 (J4).

Low Additive Jitter, Twelve LVDS Outputs Clock Buffer Evaluation Board SCAU045–September 2010