Datasheet

www.ti.com The EVM Board Schematic
Table 1. Output Control Table for CDCLVD2102
EN (Input 1) Clock Outputs
0 (GND) All outputs disabled (static "0")
OPEN All outputs enabled
1 (VDD) OUT0, OUT1 enabled and OUT2, OUT3 disabled (static "0")
9 The EVM Board Schematic
Figure 2 and Figure 3 show the printed circuit board (PCB) schematics .
Figure 2. CDCLVD1204/CDCLVD2102EVM Schematic, Sheet 1 of 2
3
SCAU043–June 2010 Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board
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