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Table Of Contents
Low Additive Jitter, Four-LVDS-Outputs Clock Buffer With Divider EVM
1 Features
1.1 General Description
1.2 Signal Path and Control Circuitry
2 Getting Started
3 Power Supply Connection
4 Input Clock Connection
5 Output Clock
6 Onboard Oscillator/VCO
7 The EVM Board Schematic
8 Bill of Materials
Important Notices
www.ti.com
The EVM
Board Schematic
Figure 2.
CDCLVD1213EVM –
Schematic 1
3
SCAU044
–
July 2010
Low-Additive Jitter,
Four-LVDS-Outputs Clock
Buffer With
Divider EVM
Copyright ©
2010, Texas
Instruments Incorporated
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