Datasheet

Signal Path and Control Circuit www.ti.com
2 Signal Path and Control Circuit
The CDCLVC1310EVM supports single-ended and differential inputs up to 200 MHz. For more information
about the CDCLVC1310, see the CDCLVC1310 data sheet available for download from the TI Web site
(www.ti.com).
3 Getting Started
The CDCLVC1310EVM has self-explanatory labeling and uses similar naming conventions as the
CDCLVC1310 product data sheet. In this user’s guide, all words in boldface and italic print reflect the
actual labeling on the EVM.
4 Power Supply Connections
Connect the first power-supply source to the banana plug labeled VDD. Connect the second power-supply
source to the banana plug labeled VDDO, and connect the ground of both power-supply sources to GND.
Decoupling capacitors and a ferrite bead isolate the EVM power from the CDCLVC1310 device power
pins.
The CDCLVC1310EVM can use a core supply voltage (VDD) of 2.375 V to 3.465 V. For output supply
voltage (VDDO) the CDCLVC1310EVM can use voltages of 1.35 V to 3.465 V.
5 Input Clock Selection
The CDCLVC1310EVM offers users the option of receiving either a differential or single-ended clock as
the clock input. A third option is to use a crystal as clock input. Therefore, the board offers three inputs
(PRI_IN, SEC_IN and XTAL input). Both the PRI_IN and the SEC_IN input can handle single-ended or
differential clocks. To use one of these inputs with a single-ended clock it is recommended to use the
recommended LVCMOS input configuration [see the CDCLVC1310 (SCAS917) data sheet].
In the default state, PRI_IN is not terminated and SEC_IN is terminated with the recommended LVCMOS
input configuration.
Any of the three input clocks can be selected using jumper J42 (IN_SEL0) and J43 (IN_SEL1). When both
jumpers are shorted to GND, PRI_IN is selected. When J42 is shorted to VDD and J43 is shorted to GND,
SEC_IN is selected. When J42 is shorted to GND and J43 is shorted to VDD, crystal input is selected.
When both jumpers are shorted to VDD, the crystal oscillator stage is bypassed and the input can be
driven by a LVCMOS input clock.
Table 1. Input Selection
J43 (IN_SEL1) J42 (IN_SEL0) INPUT CHOSEN
1-2 1-2 PRI_IN
1-2 2-3 SEC_IN
2-3 1-2 XTAL/Overdrive
(1)
2-3 2-3 XTAL Bypass
(2)
(1)
This mode enables the XTAL-Oscillator. It can be used to overdrive the XTAL-Oscillator with a
LVCMOS input (max 50-MHz).
(2)
This mode is only XTAL Bypass (max 50-MHz).
6 Output Clock
The CDCLVC1310 generates ten LVCMOS outputs. The outputs can be terminated with a Thevenin
termination. It is possible to place a capacitive load at the outputs.
In default state the outputs have a 39-Ω series termination. This termination is fitted for 3.3-V VDDO
supply.
2
10-Output Low Jitter Low Power Differential to LVCMOS Clock Buffer - SCAU046– December 2011
Evaluation Board
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