Datasheet

Y0 Y4 Y6
Y9 Y11 Y10
VDD
0
0
VDD
0
0
VDD
0
0
VDD
0
0
VDD
0
0
VDD
0
0
R20 0 R20 0
R15
NU
R15
NU
R24
NU
R24
NU
R7
Nu
R7
Nu
C8 0Ohm C8 0Ohm
C4 0Ohm C4 0Ohm
R16
Nu
R16
Nu
J4
SMA
J4
SMA
1
2
3
4
5
R14 0 R14 0
J7
SMA
J7
SMA
1
2
3
4
5
R9
NU
R9
NU
R23 0 R23 0
R18
NU
R18
NU
C5 0Ohm C5 0Ohm
R10
Nu
R10
Nu
R19
Nu
R19
Nu
J5
SMA
J5
SMA
1
2
3
4
5
R17 0 R17 0
J8
SMA
J8
SMA
1
2
3
4
5
C6 0Ohm C6 0Ohm
R12
NU
R12
NU
R8 0 R8 0
R21
NU
R21
NU
R13
Nu
R13
Nu
R22
Nu
R22
Nu
C7 0Ohm C7 0Ohm
J3
SMA
J3
SMA
1
2
3
4
5
R11 0 R11 0
C3 0Ohm C3 0Ohm
J6
SMA
J6
SMA
1
2
3
4
5
www.ti.com Schematic
Figure 2. Schematic (Page 2 of 3)
5
SCAU042–July 2010 Low Additive Phase Noise LVCMOS Clock Buffer Evaluation Board
Copyright © 2010, Texas Instruments Incorporated