Datasheet

VDD_IN
Y8 Y7 Y5 Y2 Y3 Y1
Y0 Y4 Y6 Y9 Y11
Y10
0
VDD
0
0
VDD
0
0
VDD
0
VDD
VDD
0
R3
NU
R3
NU
R6
NU
R6
NU
R43 150 R43 150
J2
SMA
J2
SMA
1
2
3
4
5
R4 0 R4 0
C20
.01uF
C20
.01uF
1 2
J21J21
1 2 3
C19
.01uF
C19
.01uF
1 2
R2
100
R2
100
C18
.1uF
C18
.1uF
1 2
C21
.01uF
C21
.01uF
1 2
C22
.01uF
C22
.01uF
1 2
R1
100
R1
100
+
C17
10uF
+
C17
10uF
J1
SMA
J1
SMA
1
2
3
4
5
D1
GREEN
D1
GREEN
12
L1 FERRITEBEAD50ohm@100MHZL1 FERRITEBEAD50ohm@100MHZ
1
2
+
C16
47uF
+
C16
47uF
CDCLVC1112
U1
CDCLVC1112
U1
CLK_IN
1
Enable
2
Y_0
3
GND
4
VDD
5
Y_4
6
GND_2
7
Y_6
8
VDD_2
9
Y_9
10
GND_3
11
Y_12
12
VDD_5
13
Y_10
14
GND_5
15
Y_8
16
Y_7
17
VDD_4
18
Y_5
19
GND_4
20
Y2
21
VDD_3
22
Y_3
23
Y_1
24
+
C15
47uF
+
C15
47uF
P1
VDD
P1
VDD
1
1
C24
.01uF
C24
.01uF
1 2
C2 0Ohm C2 0Ohm C1 0Ohm C1 0Ohm
R5
0
R5
0
P2
GND
P2
GND
1
1
C23
.01uF
C23
.01uF
1 2
Schematic www.ti.com
8 Schematic
Figure 1. Schematic (Page 1 of 3)
4
Low Additive Phase Noise LVCMOS Clock Buffer Evaluation Board SCAU042–July 2010
Copyright © 2010, Texas Instruments Incorporated