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Low Additive Phase Noise LVCMOS Clock Buffer Evaluation Board

User's Guide

SCAU042–July 2010

Low Additive Phase Noise LVCMOS Clock Buffer

Evaluation Board

NEED ABSTRACT

Contents

1 General Description ......................................................................................................... 1

1.1 Features ............................................................................................................. 1

2 Signal Path and Control Circuitry ......................................................................................... 2

3 Getting Started .............................................................................................................. 2

4 Power-Supply Connections ................................................................................................ 2

5 Enabling/Disabling the Outputs ........................................................................................... 2

6 Output Clock ................................................................................................................. 2

7 Bill of Materials .............................................................................................................. 2

8 Schematic .................................................................................................................... 4

9 References ................................................................................................................... 6

List of Figures

1 Schematic (Page 1 of 3) ................................................................................................... 4

2 Schematic (Page 2 of 3) ................................................................................................... 5

3 Schematic (Page 31 of 3).................................................................................................. 6

List of Tables

1 Bill of Materials .............................................................................................................. 2

1 General Description

The CDCLVC1112 is a high-performance, low additive phase noise LVCMOS clock buffer. It has one

LVCMOS input and twelve LVCMOS outputs. It has also an enable pin.

This evaluation module (EVM) is designed to demonstrate the electrical performance of the

CDCLVC1112.Throughout this document, the acronym EVM and the phrases evaluation module and

evaluation board are synonymous with the CDCLVC1112 EVM. Figure 1 illustrates the CDCLVC1112

EVM.

For optimum performance, the board is equipped with 50Ω SMA connectors and well controlled 50Ω

impedance microstrip transmission lines.

1.1 Features

• Easy-to-use evaluation board to fan out low phase noise

• Easy device setup

• Enable pin configurable though jumper and SMA

• Board powered at 3.3V

SCAU042–July 2010 Low Additive Phase Noise LVCMOS Clock Buffer Evaluation Board

Summary of content (7 pages)

PAGE 1
User's Guide SCAU042 – July 2010 Low Additive Phase Noise LVCMOS Clock Buffer Evaluation Board NEED ABSTRACT 2 3 4 5 6 7 8 9 Contents General Description ......................................................................................................... 1.1 Features ............................................................................................................. Signal Path and Control Circuitry .........................................................................................
PAGE 2
Signal Path and Control Circuitry 2 www.ti.com Signal Path and Control Circuitry The CDCLVC1112 EVM supports single-ended inputs up to 250MHz. For more information about the CDCLVC1112, see the CDCLVC1112 product data sheet available for download from the TI web site (www.ti.com). 3 Getting Started The CDCLVC1112EVM has self-explanatory labeling and uses similar naming conventions as the CDCLVC1112 product datasheet.
PAGE 3
Bill of Materials www.ti.com Table 1.
PAGE 4
0 GND P2 VDD P1 4 2 1 1 1 1 J2 SMA 5 3 5 3 0 1 + VDD_IN 0 Ohm C2 1 R6 NU R3 NU 0 L1 R2 100 C15 47uF 0 VDD 0 Ohm 2 C16 47uF + C17 10uF FERRITE BEAD 50 ohm @ 100MHZ 0 R4 + J21 0 C18 .1uF 1 2 3 VDD 2 1 C1 Y11 Y9 Y6 Y4 Y0 C19 .01uF R5 0 2 1 1 C20 .01uF 0 VDD 2 1 4 2 C21 .01uF 2 1 R1 100 0 C22 .01uF 2 1 Copyright © 2010, Texas Instruments Incorporated 12 11 10 9 8 7 6 5 4 3 2 1 C23 .01uF Y_10 VDD_5 C24 .
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Copyright © 2010, Texas Instruments Incorporated Y6 Y4 Y0 0 R14 0 R11 0 R8 0 Ohm C5 0 0 VDD 0 Ohm C4 0 VDD 0 Ohm C3 1 J3 SMA R15 J5 NU SMA 1 R13 Nu R12 J4 NU SMA 1 R10 Nu R9 NU R7 Nu 5 3 5 3 5 3 4 2 4 2 4 2 0 0 0 Y10 Y11 Y9 0 R23 0 R20 0 R17 0 Ohm C8 0 0 VDD 0 Ohm C7 0 VDD 0 Ohm C6 VDD R24 J8 NU SMA 1 R22 Nu R21 J7 NU SMA 1 R19 Nu R18 J6 NU SMA 1 R16 Nu 5 3 5 3 SCAU042 – July 2010 5 3 VDD 4 2 4 2 4 2 0 0 0 www.ti.
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Low Additive Phase Noise LVCMOS Clock Buffer Evaluation Board Copyright © 2010, Texas Instruments Incorporated Y5 Y7 Y8 0 Ohm C11 R32 0 0 Ohm C10 0 Ohm C9 0 R29 0 R26 0 VDD 0 VDD 0 R33 J11 NU SMA 1 R31 Nu R30 J10 NU SMA 1 R28 Nu R27 J9 NU SMA 1 R25 Nu 5 3 5 3 5 3 6 4 2 4 2 4 2 0 0 0 Y1 Y3 Y2 0 R41 0 R38 0 R35 0 Ohm C14 0 0 VDD 0 Ohm C13 0 VDD 0 Ohm C12 VDD R42 J14 NU SMA 1 R40 Nu R39 J13 NU SMA 1 R37 Nu R36 J12 NU SMA 1 R34 Nu 5 3 5 3 9 5 3
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.