Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE
- RECOMMENDED OPERATING CONDITIONS
- RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS
- EEPROM SPECIFICATION
- TIMING REQUIREMENTS
- DEVICE CHARACTERISTICS
- DEVICE CHARACTERISTICS (Continued)
- DEVICE CHARACTERISTICS (Continued)
- PARAMETER MEASUREMENT INFORMATION
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- Control Terminal Configuration
- DEFAULT DEVICE SETTING
- SDA/SCL SERIAL INTERFACE
- DATA PROTOCOL
- Generic Programming Sequence
- Byte Write Programming Sequence
- Byte Read Programming Sequence
- Block Write Programming Sequence
- Block Read Programming Sequence
- Timing Diagram for the SDA/SCL Serial Control Interface
- SDA/SCL Hardware Interface
- SDA/SCL CONFIGURATION REGISTERS
- PLL MULTIPLIER/DIVIDER DEFINITIONPLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition Section
- Revision History
CDCE949
CDCEL949
SCAS844D –AUGUST 2007–REVISED MARCH 2010
www.ti.com
REVISION HISTORY
Changes from Original (August 2007) to Revision A Page
• Changed the THERMAL RESISTANCE FOR TSSOP table ................................................................................................ 4
• Changed Table 9 RID From: 0h To: Xb .............................................................................................................................. 15
• Added note to the PWDN description,Table 9 .................................................................................................................... 15
Changes from Revision A (December 2007) to Revision B Page
• Added Note 3: SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table. .................. 3
Changes from Revision B (September 2009) to Revision C Page
• Deleted sentence - A different default setting can be programmed upon customer request. Contact Texas
Instruments sales or marketing representative for more information. ................................................................................ 10
Changes from Revision C (October 2009) to Revision D Page
• Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 foot to PLL1, PLL2, PLL3, & PLL4 Configure
Register Table ..................................................................................................................................................................... 18
• Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition Section .................................... 25
26 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE949 CDCEL949