Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE
- RECOMMENDED OPERATING CONDITIONS
- RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS
- EEPROM SPECIFICATION
- TIMING REQUIREMENTS
- DEVICE CHARACTERISTICS
- DEVICE CHARACTERISTICS (Continued)
- DEVICE CHARACTERISTICS (Continued)
- PARAMETER MEASUREMENT INFORMATION
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- Control Terminal Configuration
- DEFAULT DEVICE SETTING
- SDA/SCL SERIAL INTERFACE
- DATA PROTOCOL
- Generic Programming Sequence
- Byte Write Programming Sequence
- Byte Read Programming Sequence
- Block Write Programming Sequence
- Block Read Programming Sequence
- Timing Diagram for the SDA/SCL Serial Control Interface
- SDA/SCL Hardware Interface
- SDA/SCL CONFIGURATION REGISTERS
- PLL MULTIPLIER/DIVIDER DEFINITIONPLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition Section
- Revision History
CDCE949
CDCEL949
www.ti.com
SCAS844D –AUGUST 2007–REVISED MARCH 2010
Table 13. PLL4 Configuration Register
OFFSET
(1)
Bit
(2)
Acronym Default
(3)
DESCRIPTION
40h 7:5 SSC4_7 [2:0] 000b SSC4: PLL4 SSC Selection (Modulation Amount)
(4)
4:2 SSC4_6 [2:0] 000b Down Center
000 (off) 000 (off)
1:0 SSC4_5 [2:1]
001 – 0.25% 001 ± 0.25%
000b
010 – 0.5% 010 ± 0.5%
41h 7 SSC4_5 [0]
011 – 0.75% 011 ± 0.75%
6:4 SSC4_4 [2:0] 000b
100 – 1.0% 100 ± 1.0%
101 – 1.25% 101 ± 1.25%
3:1 SSC4_3 [2:0] 000b
110 – 1.5% 110 ± 1.5%
0 SSC4_2 [2]
111 – 2.0% 111 ± 2.0%
000b
42h 7:6 SSC4_2 [1:0]
5:3 SSC4_1 [2:0] 000b
2:0 SSC4_0 [2:0] 000b
43h
7 FS4_7 0b
FS4_x: PLL4 Frequency Selection
(4)
6 FS4_6 0b 0 – f
VCO4_0
(predefined by PLL4_0 – Multiplier/Divider value)
1 – f
VCO4_1
(predefined by PLL4_1 – Multiplier/Divider value)
5 FS4_5 0b
4 FS4_4 0b
3 FS4_3 0b
2 FS4_2 0b
1 FS4_1 0b
0 FS4_0 0b
44h PLL4 Multiplexer: 0 – PLL4
7 MUX4 1b
1 – PLL4 Bypass (PLL4 is in power down)
Output Y8 Multiplexer: 0 – Pdiv6
6 M8 1b
1 – Pdiv8
Output Y9 Multiplexer: 00 – Pdiv6-Divider
01 – Pdiv8-Divider
5:4 M9 10b
10 – Pdiv9-Divider
11 – reserved
3:2 Y8Y9_ST1 11b Y8, 00 – Y8/Y9 disabled to 3-State (PLL4 is in power down)
Y9-State0/1definition: 01 – Y8/Y9 disabled to 3-State (PLL4 on)
10 –Y8/Y9 disabled to low (PLL4 on)
1:0 Y8Y9_ST0 01b
11 – Y8/Y9 enabled (normal operation, PLL4 on)
45h
7 Y8Y9_7 0b
Y8Y9_x Output State Selection
(4)
6 Y8Y9_6 0b 0 – state0 (predefined by Y8Y9_ST0)
1 – state1 (predefined by Y8Y9_ST1)
5 Y8Y9_5 0b
4 Y8Y9_4 0b
3 Y8Y9_3 0b
2 Y8Y9_2 0b
1 Y8Y9_1 1b
0 Y8Y9_0 0b
46h PLL4 SSC down/center selection: 0 – down
7 SSC4DC 0b
1 – center
7-Bit Y8-Output-Divider Pdiv8: 0 – reset and stand-by
6:0 Pdiv8 01h
1-to-127 – divider value
47h 7 — 0b Reserved – do not write others than 0
7-Bit Y9-Output-Divider Pdiv9: 0 – reset and stand-by
6:0 Pdiv9 01h
1-to-127 – divider value
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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