Datasheet

CDCE949
CDCEL949
SCAS844D –AUGUST 2007–REVISED MARCH 2010 www.ti.com
Table 12. PLL3 Configuration Register (continued)
OFFSET
(1)
Bit
(2)
Acronym Default
(3)
DESCRIPTION
38h 7:0 PLL3_0N [11:4 PLL3_0
(5)
: 30-Bit Multiplier/Divider value for frequency f
VCO3_0
004h
(for more information see paragraph PLL Multiplier/Divider Definition)
39h 7:4 PLL3_0N [3:0]
3:0 PLL3_0R [8:5]
000h
3Ah 7:3 PLL3_0R[4:0]
2:0 PLL3_0Q [5:3]
10h
3Bh 7:5 PLL3_0Q [2:0]
4:2 PLL3_0P [2:0] 010b
f
VCO3_0
range selection: 00 – f
VCO3_0
< 125 MHz
01 – 125 MHz ≤ f
VCO3_0
< 150 MHz
1:0 VCO3_0_RANGE 00b
10 – 150 MHz ≤ f
VCO3_0
< 175 MHz
11 – f
VCO3_0
≥ 175 MHz
3Ch 7:0 PLL3_1N [11:4] PLL3_1
(5)
: 30-Bit Multiplier/Divider value for frequency f
VCO3_1
004h
(for more information see paragraph PLL Multiplier/Divider Definition)
3Dh 7:4 PLL3_1N [3:0]
3:0 PLL3_1R [8:5]
000h
3Eh 7:3 PLL3_1R[4:0]
2:0 PLL3_1Q [5:3]
10h
3Fh 7:5 PLL3_1Q [2:0]
4:2 PLL3_1P [2:0] 010b
f
VCO3_1
range selection: 00 – f
VCO3_1
< 125 MHz
01 – 125 MHz ≤ f
VCO3_1
< 150 MHz
1:0 VCO3_1_RANGE 00b
10 – 150 MHz ≤ f
VCO3_1
< 175 MHz
11 – f
VCO3_1
≥ 175 MHz
(5) PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096
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