Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE
- RECOMMENDED OPERATING CONDITIONS
- RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS
- EEPROM SPECIFICATION
- TIMING REQUIREMENTS
- DEVICE CHARACTERISTICS
- DEVICE CHARACTERISTICS (Continued)
- DEVICE CHARACTERISTICS (Continued)
- PARAMETER MEASUREMENT INFORMATION
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- Control Terminal Configuration
- DEFAULT DEVICE SETTING
- SDA/SCL SERIAL INTERFACE
- DATA PROTOCOL
- Generic Programming Sequence
- Byte Write Programming Sequence
- Byte Read Programming Sequence
- Block Write Programming Sequence
- Block Read Programming Sequence
- Timing Diagram for the SDA/SCL Serial Control Interface
- SDA/SCL Hardware Interface
- SDA/SCL CONFIGURATION REGISTERS
- PLL MULTIPLIER/DIVIDER DEFINITIONPLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition Section
- Revision History
CDCE949
CDCEL949
www.ti.com
SCAS844D –AUGUST 2007–REVISED MARCH 2010
Table 12. PLL3 Configuration Register
OFFSET
(1)
Bit
(2)
Acronym Default
(3)
DESCRIPTION
30h 7:5 SSC3_7 [2:0] 000b SSC3: PLL3 SSC Selection (Modulation Amount)
(4)
4:2 SSC3_6 [2:0] 000b Down Center
000 (off) 000 (off)
1:0 SSC3_5 [2:1]
001 – 0.25% 001 ± 0.25%
000b
010 – 0.5% 010 ± 0.5%
31h 7 SSC3_5 [0]
011 – 0.75% 011 ± 0.75%
6:4 SSC3_4 [2:0] 000b
100 – 1.0% 100 ± 1.0%
101 – 1.25% 101 ± 1.25%
3:1 SSC3_3 [2:0] 000b
110 – 1.5% 110 ± 1.5%
0 SSC3_2 [2]
111 – 2.0% 111 ± 2.0%
000b
32h 7:6 SSC3_2 [1:0]
5:3 SSC3_1 [2:0] 000b
2:0 SSC3_0 [2:0] 000b
33h
7 FS3_7 0b
FS3_x: PLL3 Frequency Selection
(4)
6 FS3_6 0b 0 – f
VCO3_0
(predefined by PLL3_0 – Multiplier/Divider value)
1 – f
VCO3_1
(predefined by PLL3_1 – Multiplier/Divider value)
5 FS3_5 0b
4 FS3_4 0b
3 FS3_3 0b
2 FS3_2 0b
1 FS3_1 0b
0 FS3_0 0b
34h PLL3 Multiplexer: 0 – PLL3
7 MUX3 1b
1 – PLL3 Bypass (PLL3 is in power down)
Output Y6 Multiplexer: 0 – Pdiv4
6 M6 1b
1 – Pdiv6
Output Y7 Multiplexer: 00 – Pdiv4-Divider
01 – Pdiv6-Divider
5:4 M7 10b
10 – Pdiv7-Divider
11 – reserved
3:2 Y6Y7_ST1 11b Y6, 00 – Y6/Y7 disabled to 3-State (PLL3 is in power down)
Y7-State0/1definition: 01 – Y6/Y7 disabled to 3-State (PLL3 on)
10 –Y6/Y7 disabled to low (PLL3 on)
1:0 Y6Y7_ST0 01b
11 – Y6/Y7 enabled (normal operation, PLL3 on)
35h
7 Y6Y7_7 0b
Y6Y7_x Output State Selection
(4)
6 Y6Y7_6 0b 0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
5 Y6Y7_5 0b
4 Y6Y7_4 0b
3 Y6Y7_3 0b
2 Y6Y7_2 0b
1 Y6Y7_1 1b
0 Y6Y7_0 0b
36h PLL3 SSC down/center selection: 0 – down
7 SSC3DC 0b
1 – center
7-Bit Y6-Output-Divider Pdiv6: 0 – reset and stand-by
6:0 Pdiv6 01h
1-to-127 – divider value
37h 7 — 0b Reserved – do not write others than 0
7-Bit Y7-Output-Divider Pdiv7: 0 – reset and stand-by
6:0 Pdiv7 01h
1-to-127 – divider value
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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