Datasheet

CDCE949
CDCEL949
SCAS844D –AUGUST 2007–REVISED MARCH 2010 www.ti.com
Table 11. PLL2 Configuration Register (continued)
OFFSET
(1)
Bit
(2)
Acronym Default
(3)
DESCRIPTION
28h 7:0 PLL2_0N [11:4 PLL2_0
(5)
: 30-Bit Multiplier/Divider value for frequency f
VCO2_0
004h
(for more information see paragraph PLL Multiplier/Divider Definition)
29h 7:4 PLL2_0N [3:0]
3:0 PLL2_0R [8:5]
000h
2Ah 7:3 PLL2_0R[4:0]
2:0 PLL2_0Q [5:3]
10h
2Bh 7:5 PLL2_0Q [2:0]
4:2 PLL2_0P [2:0] 010b
f
VCO2_0
range selection: 00 – f
VCO2_0
< 125 MHz
01 – 125 MHz ≤ f
VCO2_0
< 150 MHz
1:0 VCO2_0_RANGE 00b
10 – 150 MHz ≤ f
VCO2_0
< 175 MHz
11 – f
VCO2_0
≥ 175 MHz
2Ch 7:0 PLL2_1N [11:4] PLL2_1
(5)
: 30-Bit Multiplier/Divider value for frequency f
VCO1_1
004h
(for more information see paragraph PLL Multiplier/Divider Definition)
2Dh 7:4 PLL2_1N [3:0]
3:0 PLL2_1R [8:5]
000h
2Eh 7:3 PLL2_1R[4:0]
2:0 PLL2_1Q [5:3]
10h
2Fh 7:5 PLL2_1Q [2:0]
4:2 PLL2_1P [2:0] 010b
f
VCO2_1
range selection: 00 – f
VCO2_1
< 125 MHz
01 – 125 MHz ≤ f
VCO2_1
< 150 MHz
1:0 VCO2_1_RANGE 00b
10 – 150 MHz ≤ f
VCO2_1
< 175 MHz
11 – f
VCO2_1
≥ 175 MHz
(5) PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096
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