Datasheet

1 7 1 1 1 1 1 1
S Slave Address Wr A A Sr Rd A
8 1 1 1 1
ByteCountN A A A PDataByte0 … DataByteN-1
8
CommandCode
7
Slave Address
8 8
P S P
t
(BUS)
t
w(SCLL)
t
w(SCLH)
t
r
t
f
t
h(START)
t
SU(SDA)
t
h(SDA)
t
SU(STOP)
t
SU(START)
t
r
t
f
SCL
SDA
V
IH
V
IL
V
IH
V
IL
A
Bit7(MSB)
Bit6 Bit0(LSB)
R
P
Master
R
P
SDA
SCL
C
BUS
Slave
CDCE949
CDCEL949
C
BUS
CDCE949
CDCEL949
www.ti.com SCAS844D –AUGUST 2007–REVISED MARCH 2010
Block Read Programming Sequence
Figure 11. Block Read Protocol
Timing Diagram for the SDA/SCL Serial Control Interface
Figure 12. Timing Diagram for the SDA/SCL Serial Control Interface
SDA/SCL Hardware Interface
Figure 13 shows how the CDCE949/CDCEL949 clock synthesizer is connected to the SDA/SCL serial interface
bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the
maximum) if many devices are connected.
Note that the pull-up resistor value (R
P
) depends on the supply voltage, bus capacitance and number of
connected devices. The recommended pull-up value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at
V
OLmax
= 0.4 V for the output stages (for more details see the SMBus or I
2
C Bus specification).
Figure 13. SDA/SCL Hardware Interface
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