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User's Guide

SLAU250 – May 2008

1.5-GHz Low-Phase Noise Clock Evaluation Board

This user's guide discusses the general operation and configuration of the Texas Instruments CDCE72010

evaluation board.

Contents

1 Features ....................................................................................................................... 2

2 General Description ......................................................................................................... 2

3 Signal Path and Control Circuitry ......................................................................................... 3

4 Software Selectable Options .............................................................................................. 3

5 Installing the GUI Interface and USB Driver ............................................................................. 3

6 CDCE72010 Control GUI Interface ....................................................................................... 5

7 TI CDCE72010 Control GUI Interface .................................................................................... 5

7.1 Using Software-Enabled PLL Selection .......................................................................... 5

8 Configuring the Board ..................................................................................................... 10

8.1 Default Configuration for Programming and Testing With USB Cable Attached .......................... 10

8.2 Configuration for Programming With USB Cable Attached .................................................. 10

8.3 Configuration for Testing From a Saved Configuration With USB Cable Removed After

Programming ....................................................................................................... 10

8.4 Configuration for Onboard External Loop Filter ............................................................... 11

8.5 Configuration for PLL Lock Detect .............................................................................. 12

9 CDCE72010EVM Board Schematic Diagram .......................................................................... 13

List of Figures

1 CDCE72010EVM Board .................................................................................................... 2

2 CDCE72010EVM External Loop Filter Topology ....................................................................... 12

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Summary of content (20 pages)

PAGE 1
User's Guide SLAU250 – May 2008 1.5-GHz Low-Phase Noise Clock Evaluation Board This user's guide discusses the general operation and configuration of the Texas Instruments CDCE72010 evaluation board. 1 2 3 4 5 6 7 8 9 Contents Features ....................................................................................................................... 2 General Description .........................................................................................................
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Features 1 www.ti.com Features • • • • • • Easy-to-use evaluation board to generate low-phase noise clocks up to 1.5 GHz Easy device programming via host-powered USB port Fast configuration through provided graphical user interface (GUI) software interface Total board power provided either through USB port or separate 3.3 V and ground connections. Single-ended or differential input reference clock Crystal filter on output readily available for clocking high-speed analog-to-digital converters, if needed.
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Signal Path and Control Circuitry www.ti.com 3 Signal Path and Control Circuitry The CDCE72010 provides support for selectable tri-inputs, and two of the inputs (PRI REF and SEC REF) can accept a 8-kHz to 500-MHz frequency input from a differential signal source or a 8-kHz to 200-MHz frequency input from a single-ended signal source. The CDCE72010 provides support for up to ten differential (LVDS or LVPECL) or 20 single-ended (LVCMOS) or any combination of outputs up to 1.5 GHz.
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Installing the GUI Interface and USB Driver www.ti.com Connect the USB cable to the EVM. If The Windows™ operating system asks for an appropriate driver, do not use the automatic search option. Select a manual installation, and when prompted for the driver location, browse to the CDCE72010 GUI file folder that was used during instillation. If the Windows operating system does not ask for a driver, no action is required.
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www.ti.com 6 CDCE72010 Control GUI Interface 7 TI CDCE72010 Control GUI Interface 7.1 Using Software-Enabled PLL Selection CDCE72010 Control GUI Interface The illustration in the software shows the block diagram of the CDCE72010. In this illustration, the user can change the Input Frequency, Input Divider, Input type, Input selection, PFD Charge Pump, Output Divider, and Output type. The rest are selected by the software with user-selectable options as described in the steps below.
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TI CDCE72010 Control GUI Interface www.ti.com Step 1: External Control Pins Selection Before programming the PLL, select the External Control Pins button in the EVM Status section of the GUI. The selections on this popup window, as shown in the following illustration, must be selected according to the desired working configuration of the CDCE72010. 6 1.
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www.ti.com TI CDCE72010 Control GUI Interface Step 2: Primary/Secondary Reference Input Selection The primary or the secondary reference input buffer section on the GUI can be clicked for a popup window that opens up, as shown in the following illustration.
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TI CDCE72010 Control GUI Interface www.ti.com Step 4: PFD and Charge Pump Selection The PFD and Charge Pump section of the GUI can be clicked for a popup window that opens up. The following illustration shows selections on the charge pump current and charge pump pulse width. Step 5: Output Divider The CDCE72010 has 10 outputs and 8 Output Dividers. Outputs 0 and 1 share the same divider, and outputs 8 and 9 share the same divider.
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www.ti.com TI CDCE72010 Control GUI Interface Step 6: Output Type Selection The Output Buffer section of the GUI for each of the five outputs can be clicked for a popup window that opens up, as displayed in the following illustration. For each output clock source, the user can select LVPECL, LVPECL High Swing (in which cases the output 150-Ω termination is automatically enabled), LVDS, LVDS High Swing, or LVCMOS. In CMOS mode, the P and N outputs become separate CMOS outputs running at the same frequency.
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Configuring the Board 8 www.ti.com Configuring the Board The CDCE72010EVM can be powered from the USB power supply or from an external source. The CDCE72010EVM only needs a USB cable attached for programming purposes. However, for test measurements, it is recommended to also use an external 3.3-V power supply. Test measurements also can be taken with only the USB-supplied power. However, due to USB port power limitations, results may degrade.
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Configuring the Board www.ti.com Configuration for Onboard Reference Input Biasing. If the on-chip biasing is not used in the CDCE72010 for AC-coupled reference input signals for PRI_REF or SEC_REF, the CDCE72010EVM alternately can be set up to provide onboard biasing for LVPECL or LVDS inputs. These bias voltages of 1.2 V for LVDS and 1.9 V for LVPECL are derived from the onboard voltage divider.
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Configuring the Board www.ti.com The external loop filter can be chosen by selecting one from the four available options on the CDCE72010EVM using the dip switches, SW9 and SW10, located at the back side of the EVM as shown in the following illustration. The four options are Filter1 = 1 kHz, Filter2 = 520 Hz, Filter3 = 120 Hz, and Filter4 = 15 Hz. Figure 2. CDCE72010EVM External Loop Filter Topology 8.
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www.ti.com 9 CDCE72010EVM Board Schematic Diagram CDCE72010EVM Board Schematic Diagram SLAU250 – May 2008 Submit Documentation Feedback 1.
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CDCE72010EVM Board Schematic Diagram 14 1.5-GHz Low-Phase Noise Clock Evaluation Board www.ti.
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www.ti.com SLAU250 – May 2008 Submit Documentation Feedback CDCE72010EVM Board Schematic Diagram 1.
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CDCE72010EVM Board Schematic Diagram 16 1.5-GHz Low-Phase Noise Clock Evaluation Board www.ti.
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www.ti.com SLAU250 – May 2008 Submit Documentation Feedback CDCE72010EVM Board Schematic Diagram 1.
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CDCE72010EVM Board Schematic Diagram 18 1.5-GHz Low-Phase Noise Clock Evaluation Board www.ti.
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EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.