Datasheet

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device SRAM. If LVPECL output is desired, scroll through the Output type box until LVPECL is
displayed. This option automatically enables onboard LVPECL termination. If LVDS output is desired,
scroll through the Output type box until LVDS is displayed.
Step 4. PLL Bandwidth Select
If the user wants to adjust the PLL bandwidth, the Loop Filter block must be clicked. Clicking this block
brings up a pop-up screen, as shown in Figure 6 .
Figure 6. Loop Filter Configuration Pop-Up Dialog
For a clean reference input to CDCE421A (such as from an oscillator or crystal), the maximum
bandwidth and phase margin settings must be used, or 400 kHz and 80 degrees, respectively. The
PDF charge pump current must be set to its maximum (224 µ A). The PFD charge pump current can be
set by clicking on the PDF Charge Pump block. This selection then presents a drop-down menu with
the various charge pump current settings.
For a dirty reference input to CDCE421A, use the minimum bandwidth setting (50 kHz). Additionally, to
reduce the output jitter for a dirty input, the phase margin can be reduced to near-minimum (30
degrees), depending on the integration limits of the jitter that is deemed important for a given
application. To reduce the output jitter even further, reduce the charge pump current to near-minimum
(56 µ A), depending on the integration limits of the jitter.
Step 5. Write to CDCE421A EEPROM
To write any particular setting to the EEPROM (in locking or no-locking mode), the menu item at the
top of the GUI titled Device_EEPROM must be clicked. This action highlights the items Write settings
to EEPROM (No locking) and Write settings to EEPROM (Locking) as part of a drop-down menu.
Choose the appropriate option after setting the desired PLL configurations in order to write to the
EEPROM in the appropriate mode.
10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board8 SCAU031 – June 2009
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