Datasheet

6 Chronos GUI Software
6.1 Using Software-Enabled Automatic PLL Selection
www.ti.com Chronos GUI Software
Figure 5 illustrates the TI Chronos GUI software display.
Figure 5. TI Chronos GUI Window
The screenshot displayed in Figure 5 shows the on-chip PLL structure of the CDCE421A. In this display,
the user can change the Input Frequency, PFD Charge Pump, Loop Filter, and Output settings. The
balance of the settings are selected by the software with user-selectable options as described in the steps
below.
Step 1. IC Config and Input Calculator
Before programming the PLL, the EVM block that is being programmed must be selected in the IC
Block Config section of the GUI. For any block in the EVM that is being used, the first row of
calculations is useful when trying to investigate the input frequency to the CDCE421A required in order
to obtain a desired output frequency. The input is found by pressing the Calculate button.
Step 2. Store Crystal Frequency
If a crystal input is used in Block B of the EVM, the crystal frequency must be entered into the space
provided by clicking on the Device_EEPROM field found at the top of the software GUI. This action
opens a drop-down menu, where the user can click the menu item labeled Save Block B – XTAL Freq
to EEPROM. In this field, enter the crystal frequency in the format xx.xxx,specified in MHz.
Step 3. Output Calculator and Apply PLL Settings
The second row of calculations is used to get the PLL settings required to obtain a particular output
frequency provided by a given input frequency to CDCE421A. The input must be entered in the second
row as well as the place provided at the input of the PLL block diagram. After the Calculate button is
pressed, the adjacent drop-down menu is populated with several choices for the given input; the
desired output can then be chosen from this list. Choosing an output then sets the divider settings
within the PLL. Click on the Apply button (next to the drop-down menu) to write the PLL settings to the
SCAU031 – June 2009 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board 7
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