Datasheet

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1 General Description ......................................................................................................... 3
2 Signal Path and Control Circuitry .......................................................................................... 3
3 Block Description ............................................................................................................ 4
4 Software-Selectable Options ............................................................................................... 4
5 Installing the GUI Software and USB Driver ............................................................................. 5
6 Chronos GUI Software ...................................................................................................... 7
7 Configuring the Board ..................................................................................................... 10
8 Schematics and Layout .................................................................................................... 11
List of Figures
1 CDCE421A Evaluation Board .............................................................................................. 1
2 Enabled (Block A) and Disabled (Blocks B, C, D) Switch Positions .................................................. 3
3 Software Installation Screen 1 ............................................................................................. 5
4 Software Installation Screen 2 ............................................................................................. 6
5 TI Chronos GUI Window .................................................................................................... 7
6 Loop Filter Configuration Pop-Up Dialog ................................................................................. 8
7 CDCE421A Advanced Controls Pop-Up Dialog ......................................................................... 9
8 JP1 Settings ................................................................................................................. 11
9 CDCE421AEVM—Schematic ............................................................................................. 12
10 CDCE421AEVM—Schematic ............................................................................................. 13
11 CDCE421AEVM—Schematic ............................................................................................. 14
12 CDCE421AEVM—Schematic ............................................................................................. 15
13 CDCE421AEVM—Schematic ............................................................................................. 16
2 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board SCAU031 – June 2009
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