Datasheet

+3V3
+3V3
VDD
VDD
VDD
VDD
+3V3
OPAMP_EN_D
OPAMP_RD_D
LVPECL_TERM_D
CE_D
SDATA_D
VDD_D_ON
1 2
R122
422
R122
422
1 2
R88
10k
R88
10k
1
2
R1
15100k
R1
15100k
Q15 FDV303N Q15 FDV303N
12
R64
150
R64
150
2
3
4
5
1
J23
SMA-VERT
J23
SMA-VERT
1
2
R106
301
R106
301
1
2
R87
0
R87
0
1 2
R123
422
R123
422
C105
0.1uF
C105
0.1uF
12
R62
150
R62
150
Q13
FDV303N
Q13
FDV303N
D30
LEDGREEN
D30
LEDGREEN
CE
1
VCC
6
OUTN
5
OUTP
4
GND
3
SDA
TA
2
SPARE
7
U13
CDCE421_SOCKET
U13
CDCE421_SOCKET
1
2
R98 0R98 0
1 2
R83
10k
R83
10k
2
3
4
5
1
J13
SMA-VERT
J13
SMA-VERT
C107
0.1uF
C107
0.1uF
3
1
2
Q8
2N2222A
Q8
2N2222A
1 2
8 7
3 4
6 5
SW4
TDA04H0SK1
SW4
TDA04H0SK1
1 2
R102
10k
R102
10k
C55 0.1uFC55 0.1uF
C53
0.1uF
C53
0.1uF
1
2
R116 10kR116 10k
+IN
3
NC1
1
SHDN
8
OUT
6
V+
7
-IN
2
V
-
4
NC2
5
U14
TL
V3501
U14
TL
V3501
C54
0.1uF
C54
0.1uF
C46
1uF
C46
1uF
Schematics and Layout www.ti.com
Figure 13. CDCE421AEVM—Schematic
16 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board SCAU031 – June 2009
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