Datasheet

+3V3
+3V3
VDD
VDD
VDD
VDD
+3V3
OPAMP_EN_C
OPAMP_RD_C
LVPECL_TERM_C
CE_C
SDATA_C
VDD_C_ON
OUTPUT
+IN
3
NC1
1
SHDN
8
OUT
6
V+
7
-IN
2
V-
4
NC2
5
U15
TLV3501
U15
TLV3501
1 2
R121
422
R121
422
CE
1
VCC
6
OUTN
5
OUTP
4
GND
3
SDA
TA
2
SP
ARE
7
U12
CDCE421_OSC
U12
CDCE421_OSC
C52
0.1uF
C52
0.1uF
C117
0.1uF
C117
0.1uF
1 2
R90
10k
R90
10k
C61 0.1uFC61 0.1uF
1
2
R111
100k
R111
100k
1 2
R101
10k
R101
10k
12
R57
150
R57
150
1
2
R105
301
R105
301
Q17 FDV303N Q17 FDV303N
1 2
8 7
3 4
6 5
SW3
TDA04H0SK1
SW3
TDA04H0SK1
D29
LEDGREEN
D29
LEDGREEN
2
3
4
5
1
J22
SMA-VERT
J22
SMA-VERT
1
2
R84 0R84 0
2
3
4
5
1
J217
SMA-VERT
J217
SMA-VERT
C47
1uF
C47
1uF
Q11
FDV303N
Q11
FDV303N
2
3
4
5
1
J12
SMA-VERT
J12
SMA-VERT
1 2
R120
422
R120
422
3
1
2
Q7
2N2222A
Q7
2N2222A
1 2
R89
10k
R89
10k
1
2
R96
0-NP
R96
0-NP
1
2
R114 10kR114 10k
1
2
R86
100k-NP
R86
100k-NP
12
R63
150
R63
150
C108
0.1uF
C108
0.1uF
C116
0.1uF
C116
0.1uF
C51
0.1uF
C51
0.1uF
www.ti.com Schematics and Layout
Figure 12. CDCE421AEVM—Schematic
SCAU031 – June 2009 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board 15
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