Datasheet

+3V3
VDD
VDD
VDD
+3V3
VDD_B_ON
OUTPUT
+IN
3
NC1
1
SHDN
8
OUT
6
V+
7
-IN
2
V-
4
NC2
5
U16
TLV3501
U16
TLV3501
1
SMA-VERTSMA-VERT
1
2
R104
301
R104
301
1
SMA-VERTSMA-VERT
12
R54
150
R54
150
1 2
R92
10k
R92
10k
C62 0.1uFC62 0.1uF
D28
LEDGREEN
D28
LEDGREEN
1
2
R108
100k
R108
100k
1 2
8 7
3 4
6 5
SW2
TDA04H0SK1
SW2
TDA04H0SK1
1
2 3
4 5
6
XXMhz1 Crystal XXMhz1 Crystal
C63
1uF
C63
1uF
1 2
R100
10k
R100
10k
Q9
FDV303N
Q9
FDV303N
1 2
R1
18
422
R1
18
422
Q16 FDV303N Q16 FDV303N
1 2
R91
10k
R91
10k
3
1
2
Q6
2N2222A
Q6
2N2222A
12
R56
150
R56
150
C109
0.1uF
C109
0.1uF
C106
0.1uF
C106
0.1uF
C48
0.1uF
C48
0.1uF
1 2
R1
19
422
R1
19
422
CE
1
VCTL
14
VCC1
16
VCC2
17
TESTEN
19
SCANEN
15
SCANIN
24
OUTN
7
OUTP
10
GND1
8
GND2
9
TESTOUTA
20
SCANOUT
18
SDA
TA
3
XIN1
21
XIN2_XO
22
XIN2_VCXO
23
NC1
2
NC2
4
NC3
5
NC4
6
NC5
11
NC6
12
NC7
13
PWRPAD
25
U9
CDCE421_24QFN
U9
CDCE421_24QFN
1
2
R110 10kR110 10k
C49
0.1uF
C49
0.1uF
C110
0.1uF
C110
0.1uF
+3V3
VDD
OP
AMP_EN_B
OPAMP_RD_B
L
VPECL_TERM_B
CE_B
SDATA_B
2
3
4
5
1
J212
SMA-VERT
J212
SMA-VERT
2
3
4
5
J21J21
2
3
4
5
J11J11
Schematics and Layout www.ti.com
Figure 11. CDCE421AEVM—Schematic
14 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board SCAU031 – June 2009
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