Datasheet

VDD
+3V3
+3V3
VDD
VDD
VDD
VDD
+3V3
OP
AMP_EN_A
OP
AMP_RD_A
CE_A
SDATA_A
LVPECL_TERM_A
VDD_A_ON
REF.AINPUT
12
R58
150
R58
150
1 2
R1
13
422
R1
13
422
1 2
R1
12
422
R1
12
422
12
R68
10K-NP
R68
10K-NP
2
3
4
5
1
J14
SMA-VERT
J14
SMA-VERT
2
3
4
5
1
J24
SMA-VERT
J24
SMA-VERT
12
R61
10K-NP
R61
10K-NP
1
2
R103
301
R103
301
C64
1uF
C64
1uF
12
R70
49.9
R70
49.9
Q18 FDV303N Q18 FDV303N
12
R55
150
R55
150
D27
LEDGREEN
D27
LEDGREEN
1 2
R94
10k
R94
10k
1 2
R99
10k
R99
10k
C59
0.1uF
C59
0.1uF
3
1
2
Q5
2N2222A
Q5
2N2222A
C60
0.1uF
C60
0.1uF
2
3
4
5
1
J100
SMA-VERT
J100
SMA-VERT
C111
0.1uF
C111
0.1uF
+IN
3
NC1
1
SHDN
8
OUT
6
V+
7
-IN
2
V-
4
NC2
5
U17
TLV3501
U17
TLV3501
1
2
R109 10kR109 10k
1 2
8 7
3 4
6 5
SW1
TDA04H0SK1
SW1
TDA04H0SK1
C70
0.1uF
C70
0.1uF
Q10
FDV303N
Q10
FDV303N
CE
1
VCTL
14
VCC1
16
VCC2
17
TESTEN
19
SCANEN
15
SCANIN
24
OUTN
7
OUTP
10
GND1
8
GND2
9
TESTOUTA
20
SCANOUT
18
SDATA
3
XIN1
21
XIN2_XO
22
XIN2_VCXO
23
NC1
2
NC2
4
NC3
5
NC4
6
NC5
11
NC6
12
NC7
13
PWRPAD
25
U11
CDCE421_24QFN
U11
CDCE421_24QFN
1
2
R107
100k
R107
100k
1 2
R95
10k
R95
10k
C112
0.1uF
C112
0.1uF
C65 0.1uFC65 0.1uF
www.ti.com Schematics and Layout
Figure 10. CDCE421AEVM—Schematic
SCAU031 – June 2009 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board 13
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