User's Guide SCAU031 – June 2009 10.9-MHz to 1.175-GHz, Low Phase Noise Clock Evaluation Board Figure 1. CDCE421A Evaluation Board Features: • Easy-to-use evaluation board to generate low phase noise clocks between 10.9 MHz and 1.175 GHz • Easy device programming via host-powered USB port • Fast configuration through GUI software interface • Total board power provided either through USB port or separate 3.
www.ti.com 1 2 3 4 5 6 7 8 General Description ......................................................................................................... 3 Signal Path and Control Circuitry .......................................................................................... 3 Block Description ............................................................................................................ 4 Software-Selectable Options .......................................................................
General Description www.ti.com 1 General Description The CDCE421A is a high-performance, low phase noise clock generator. It has two fully integrated, low-noise, LC-based voltage-controlled oscillators (VCOs) that operate in the range of 1.75 GHz to 2.35 GHz. The CDCE421A has an integrated crystal oscillator circuitry that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. A 3.
Block Description 3 www.ti.com Block Description This section summarizes the function of each block. 3.1 Block A Block A includes a CDCE421A QFN device that accepts an LVCMOS reference input through the vertical SMA input connector (Ref Input), which is already ac-coupled onboard the EVM. 3.2 Block B This block includes a CDCE421A QFN device that uses an AT crystal. This block can be used as either a crystal oscillator (XO) or a voltage-controlled crystal oscillator (VCXO).
Installing the GUI Software and USB Driver www.ti.com 5 Installing the GUI Software and USB Driver To start the software installation, run the CDCE421A Control GUI v 1.0.msi, software, available in the CDCE421A product folder on TI.com. The screen shown in Figure 3 appears. Figure 3. Software Installation Screen 1 SCAU031 – June 2009 Submit Documentation Feedback 10.9-MHz to 1.
Installing the GUI Software and USB Driver www.ti.com Note the location of the installation folder because the USB driver must be installed to the same folder after setup completes and the USB cable is connected, as indicated in Figure 4. Figure 4. Software Installation Screen 2 After the setup wizard completes, start the GUI interface from the Windows® Start menu (Start→Texas Instruments→Chronos Eval↑TIChronosGUI.exe). Connect the USB cable to the EVM.
Chronos GUI Software www.ti.com 6 Chronos GUI Software Figure 5 illustrates the TI Chronos GUI software display. Figure 5. TI Chronos GUI Window 6.1 Using Software-Enabled Automatic PLL Selection The screenshot displayed in Figure 5 shows the on-chip PLL structure of the CDCE421A. In this display, the user can change the Input Frequency, PFD Charge Pump, Loop Filter, and Output settings.
Chronos GUI Software www.ti.com device SRAM. If LVPECL output is desired, scroll through the Output type box until LVPECL is displayed. This option automatically enables onboard LVPECL termination. If LVDS output is desired, scroll through the Output type box until LVDS is displayed. Step 4. PLL Bandwidth Select If the user wants to adjust the PLL bandwidth, the Loop Filter block must be clicked. Clicking this block brings up a pop-up screen, as shown in Figure 6. Figure 6.
Chronos GUI Software www.ti.com 6.2 Manual PLL Block Selection (Advanced Control) This GUI helps users to set the PLL without having to manually alter all the blocks individually within the PLL. If a user is familiar with the general operation of PLLs, one may activate individual control of the PLL blocks by clicking on the Advanced Control button. A new window appears, as shown in Figure 7. Figure 7.
Configuring the Board www.ti.com Table 1. Advanced Control: Software Setting Options (continued) Section Function Loop Filter Selects the loop filter C and R values. See screen shotsxx for recommended configurations. VCO Calibration TI Test Use This setting should be kept at 0000 ibias_100ua. Other settings are for TI internal use only. Chronos IC Config • Select Use U13 programming socket for rapid programming of Chronos-enabled devices.
Schematics and Layout www.ti.com 7.2 Configuration for Programming (with USB Cable Attached) The CDCE421AEVM can also use power supplied through the USB cable as its sole power source. However, as mentioned earlier, because of power-supply variances in the USB supply, this configuration is not recommended for measurements.
J3 D8 D9 +5V 5 RESET1 1 2 3 4 1 2 R30 1.5k 2 24LC512 A0 Vcc A1 WP A3 SCL Vss SDA 2 0.1uF U4 C28 1uF C43 R21 15K 8 7 6 5 +5V C40 +3V3 U1 1 R4 2 2 33pF 33pF EEPROM_WP SCL SDA 2 R50 1M C29 RESET# SENSE OUT2 OUT1 21 12 11 14 13 15 16 20 19 18 17 +3V3 R49 1.5k +3V3 MMBT4401 NPN 2N2222A Q1 PUR 3 TPS77333DGK GND EN# IN2 IN1 U2 R51 1.5k +3V3 2 C32 1 1 SCL SDA 1.
CE_A 6 3 VDD R61 10K- NP TDA04H0SK1 5 7 2 4 8 C70 0.1uF R70 49.9 REF. A INPUT 1 J100 SMA-VERT LVPECL_TERM_A SDATA_A 2 3 4 5 1 1 2 VDD 1 2 SW1 1 2 R68 10K- NP R113 422 2 1 VDD R112 422 2 1 1 301 2 2 4 5 6 19 15 24 14 23 22 21 1 3 1 NC1 NC2 NC3 NC4 C112 GND1 GND2 OUTP OUTN VCC1 VCC2 25 11 12 13 VDD_A_ON R58 150 FDV303N Q10 Q5 2N2222A R99 10k CDCE421_24QFN VDD PWRPAD NC5 NC6 NC7 18 20 8 9 10 7 16 17 0.1uF 0.
5 4 6 5 1 0.1uF C106 3 4 Crystal 6 3 2 XXMhz1 7 2 TDA04H0SK1 8 SW2 1 1 J212 SMA-VERT LVPECL_TERM_B SDATA_B CE_B VDD 2 3 4 5 R118 422 2 1 R119 422 2 1 301 2 R100 10k 2 4 5 6 19 15 24 14 23 22 21 1 3 D28 LED GREEN R104 VDD 1 C63 1uF GND1 GND2 OUTP OUTN VCC1 VCC2 NC1 NC2 NC3 NC4 CDCE421_24QFN PWRPAD NC5 NC6 NC7 25 11 12 13 18 20 8 9 10 7 16 17 0.1uF 0.
VDD J217 LVPECL_TERM_C SDATA_C CE_C SMA-VERT 2 3 4 5 1 2 0.1uF C108 R86 100k -NP 1 5 4 TDA04H0SK1 6 7 2 3 8 1 SW3 2 2 R121 R120 422 422 2 1 R84 0 1 R96 0 -NP 1 1 301 2 3 2 7 1 1 1uF C47 C117 OUTP OUTN VCC VDD_C_ON R63 150 FDV303N Q11 Q7 2N2222A R101 10k VDD 4 5 6 0.1uF 0.
LVPECL_TERM_D SDATA_D CE_D VDD 5 4 TDA04H0SK1 6 7 2 3 8 1 SW4 R123 422 2 1 2 2 R122 422 R87 0 R98 0 1 1 3 2 7 1 1 301 2 C46 OUTP OUTN VCC 1uF CDCE421_SOCKET GND SDATA SPARE CE U13 D30 LED GREEN R106 1 100k 4 5 6 VDD_D_ON R64 150 FDV303N Q13 Q8 2N2222A R102 10k VDD 0.1uF 0.1uF C105 C107 R115 2 1 R116 10k 1 2 3 2 2 1 +3V3 2 1 R83 10k 1 2 VDD 2 1 2 1 1 10.9-MHz to 1.
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